Digital Error Correction Logic Research Articles

Digital Error Correction Logic for Pipelined ADC Using 1.5Bits/Stage

Low power, high resolution and high-speed ADCs are becoming increasingly important with advancements in portable electronics, from mobile phones and pagers to CD players and MP3 players. This is certainly not feasible on a handheld device which is why new ADC techniques must be developed. They are becoming increasingly attractive to major data converter manufacturers and their designers because pipeline ADCs provide an optimal balance of scale, speed, resolution, power dissipation and analogue design effort. Because of latency and errors in comparators & gain stages in pipelined ADCs, the need arises for digital error correction mechanism. The digital error correction logic will be implemented for 8-bit ADC using 1.5 bits per stage. While designing we are considering important parameters of CMOS like propagation delay performance and power dissipation. The VLSI realization of digital arithmetic is implemented using TANNER EDA software tool using 0.18µm CMOS process.

A 4.06 mW 10-bit 150 MS/s SAR ADC With 1.5-bit/cycle Operation for Medical Imaging Applications

This paper reports a 10-bit 150 MS/s successive approximation register analog-to-digital converter with binary-scaled redundancy-facilitated error correction technique. The proposed 1.5-bit/cycle technique with built-in capacitive digital-to-analog converter (CDAC) redundancy, corrects multiple erroneous decisions in a total of nine conversion cycles. The proposed binary-scaled redundancy provides a 12.5% error tolerance range for the incomplete CDAC voltage settling. The digital error-correction logic circuit presented uses a bit-overlap-and-add technique. The prototype chip was fabricated in 65-nm CMOS technology and occupies chip area of 0.038 mm2. It consumes 4.06 mW from a 1.2 V supply, achieving the Nyquist signal-to-noise-and-distortion ratio of 57.81 dB and the effective number of bits of 9.31-bit at an operating frequency of 150 MS/s, corresponding to the figure-of-merit of 42.6 fJ/ conversion-step.

An 8-bit 2 GS/s 80 mW high accurate CMOS folding A/D converter with a symmetrical zero-crossing technique

An 8-bit 2 GS/s 80 mW low power and high accurate CMOS folding A/D converter with a 45 nm CMOS process is described. In order to improve the non-linearity error of a conventional folding amplifier, a new symmetrical zero-crossing technique is proposed. Further, a digital error correction logic to rectify the distortion errors of analog blocks is also discussed. The proposed chip has been fabricated with 1.2 V 45 nm Samsung CMOS technology. The effective chip area is 1.98 mm2 and the power dissipation is about 80 mW. The measured result of SNDR is about 38 dB, when the input frequency is 1 GHz at the sampling frequency of 2 GS/s. The measured INL is within +2.5 LSB/?2.0 LSB and DNL is within +1.0 LSB/?1.0 LSB.

Low power 9-bit pipelined A/D and 8-bit self-calibrated D/A converters for a DSP system

Abstract A low power, low voltage current mode 9 bit pipelined a/d converter and 8 bit self-calibrated d/a converter to interface a DSP system are presented in the paper. The a/d converter is built of 1.5 bit stages with digital error correction logic. The d/a converter is composed of 3 LSBs fine and 5 MSBs coarse current mode converters. The a/d and d/a converters were designed in 0.35 μm technology, then fabricated to verify the proposed concept. The performances of both converters are compared to the performances of known converter structures. The main advantages of the proposed converters are low power consumption and small chip area.

An 8-b 1GS/s Fractional Folding CMOS Analog-to-Digital Converter with an Arithmetic Digital Encoding Technique

A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is 2.1 mm 2 (ADC core : 1.4 mm 2 , calibration engine : 0.7

A 10-b 500 MS/s CMOS Folding A/D Converter with a Hybrid Calibration and a Novel Digital Error Correction Logic

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 ㎚ 1P6M CMOS has a DNL of ±0.8 LSB and an INL of ±1.0 LSB. The measured SNDR is 52.34-㏈ and SFDR is 62.04-㏈c when the input frequency is 78.15 ㎒ at 500 MS/s conversion rate. The SNDR of the ADC is 7-㏈ higher than the same circuit without the proposed calibration. The effective chip area is 1.55 ㎟, and the power dissipates 300 ㎽ including peripheral circuits, at a 1.2/1.5 V power supply.