Digital Code Word Research Articles

An Ultra-Low-Power Analog Multiplier-Divider Compatible with Digital Code for RRAM-Based Computing-in-Memory Macros.

This manuscript presents an ultra-low-power analog multiplier-divider compatible with digital code words, which is applicable to the integrated structure of resistive random-access memory (RRAM)-based computing-in-memory (CIM) macros. Current multiplication and division are accomplished by a current-mirror-based structure. Compared with digital dividers to achieve higher precision and operation speed, analog dividers present the advantages of a reduced power consumption and a simple circuit structure in lower precision operations, thus improving the energy efficiency. Designed and fabricated in a 55 nm CMOS process, the proposed work is capable of achieving 8-bit precision for analog current multiplication and division operations. Measurement results show that the signal delay is 1 μs when performing 8-bit operation, with a bandwidth of 1.4 MHz. The power consumption is less than 6.15 μW with a 1.2 V supply voltage. The proposed multiplier-divider can increase the operation capacity by dividing the input current and digital code while reducing the power consumption and complexity required by division, which can be further utilized in real-time operation of edge computing devices.

A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems

An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented. The proposed architecture is based on an all-digital multiplying delay-locked loop (MDLL) to provide fast locking time and multiplied output clock frequency. The proposed MDLL has two operation modes: TDC tracking and sequential tracking. At the beginning of the operation, the MDLL utilizes a cyclic Vernier time-to-digital converter (TDC) to detect the initial phase error between the reference clock and the output clock. Then the TDC generates a digital code word (DCW) for controlling the digitally controlled oscillator (DCO) to achieve a fast lock time. The gains of TDC and DCO are designed to match well with each other, enabling phase and frequency locking in only two searches in the TDC tracking mode. After locking, the TDC is turned off, and the MDLL performs the sequential tracking mode and minimizes jitter by using the delta-sigma modulator (DSM)-based dithering jitter reduction scheme. The prototype all-digital MDLL is fabricated in a 40-nm CMOS process and achieves a fast lock time of less than six reference clock cycles at 1.6 GHz from a 100 MHz reference clock. Even when the 100 MHz reference clock has a relatively high RMS jitter of 2.19 ps (peak-to-peak jitter =15.74 ps), the measured RMS and peak-to-peak jitter values of the 1.6 GHz MDLL output clock are only 2.75 ps and 23.01 ps, respectively. The proposed all-digital MDLL occupies an active area of only 0.024 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and dissipates 3.56 mW at 1.6 GHz.

A Highly-Efficient Multi-Band Multi-Mode All-Digital Quadrature Transmitter

A novel highly-efficient multi-band multi-mode all-digital quadrature transmitter is presented. In the transmitter, a switching-mode power amplifier (PA), also referred to as digital power amplifier (DPA), which consists of an in-phase PA (I-PA) and a quadrature PA (Q-PA), is controlled by the digital codewords based on an input signal to turn on and off the power cells inside the I-PA or the Q-PA. Due to the load interaction between the I-PA and the Q-PA, a 2-dimensional (2-D) digital pre-distortion (DPD) is applied to linearize the DPA. The whole transmitter is implemented in 40 nm CMOS LP process and occupies a die area of 0.7 mm2. The all-digital quadrature transmitter can support 20 MHz, 40 MHz, and 80 MHz WiFi signals, Band 38 and Band 40 LTE signals with class 3 output power, and Bluetooth BDR, EDR2, and EDR3 signals.

Digital power amplifier: A new way to exploit the switched-capacitor circuit

A digital power amplifier (DPA) that uses switched-capacitor circuits in 90 nm CMOS to efficiently amplify signals with large peak-toaverage power ratios is described in this article. In traditional DPAs, a digital code word representing a desired output envelope voltage is used to control a combination of wide-dynamic range current sources. In contrast, the switched-capacitor power amplifier (SCPA) provides a linear output characteristic by using the digital code word to selectively switch or not switch a bank of integrated capacitors at the RF carrier frequency. Therefore, the SCPA combines the functionalities of an envelope DAC and a power amplifier, and achieves excellent efficiency and output power levels. The SCPA benefits from CMOS transistor scaling, which makes RF SOC integration realizable.

Dynamic Dac Testing by Registration of the Input Code Wordin Equality When the Dac Output Matches a Reference Signal

The characterization of high resolution Digital to Analog Converter (DAC) involves new problems caused by their high performance. This paper presents a new method for measuring the characteristics of high resolution DACs under dynamic condition. The main principle of the proposed method is the conversion of the DAC analog output voltage to a digital code. The one that is corresponding to the equality of the DAC output voltage and reference signal by using a fast comparator, a dithering DAC and an accurate dc voltmeter. The output of the comparator is used as the control signal to register the digital input code word of the DAC in a fast memory. After digital processing the registered record of digital code words is used to determine the Integral-nonlinearity (INL) and Differential-nonlinearity (DNL) of the DAC under test.

Design of a digitally controlled oscillator for a Delta-Sigma phase-locked loop in a 0.13 µm CMOS-process

In this paper three different oscillator topologies are investigated. The oscillator is to be used in an all-digital phase-locked loop for frequency synthesis for the ISM/SRD license-free frequency bands at 315.0 MHz, 433.9 MHz and 868.3 MHz. The oscillator's frequency range is 75 MHz to 80 MHz and its frequency is controlled via a digital code word.

FULLY PROGRAMMABLE UNIVERSAL FILTER WITH INDEPENDENT GAIN-ω0-Q CONTROL BASED ON NEW DIGITALLY PROGRAMMABLE CMOS CCII

A fully programmable second-order universal filter with independently controllable characteristics is presented in this paper. The proposed filter is based on a new ± 0.75 V second-generation current conveyor with digitally programmable current gain. The input stage of the current conveyor is realized using two complementary MOS differential pairs to ensure rail-to-rail operation. The output stage consists of a Class-AB CMOS push-pull network, which guarantees high current driving capability with a 47.2 μA standby current. The digital programmability of the current conveyor, based on transistor arrays and MOS switches, provides variable current gain using a digital code-word. Two approaches for implementing current conveyors with programmable current gain either greater or less than one are described. The fully programmable universal filter and the proposed digitally programmable current conveyor circuits are simulated using PSPICE with 0.25 μm CMOS technology from MOSIS.

Subpicosecond jitter in picosecond electron bunches

We have simulated and measured 60–120fs time jitter of photoelectron pulses emitted by a nitride photocathode at 100GHz rate as in order to evaluate the resolution performance of a previously proposed photonic analog to digital converter. Recently, there has been an increasing demand for high speed analog-to-digital converters (ADCs) for microwave bandwidth signals. State of the art electronic ADCs have reached 10Gigasamples∕second (GS/s), 6–12bit performance [P. W. Juodawlkis, J. C. Twichell, G. E. Betts, J. J. Hargreaves, R. D. Younger, J. L. Wasserman, F. J. O’Donnell, K. G. Ray, and R. C. Williamson, IEEE Microwave Theory Tech. 49, 1840 (2001)]. We have previously introduced a photoelectronic ADC implementation with measured performance of 3bits at 100GS∕s [K. Ioakeimidi, R. Leheny, S. Gradinaru, K. Ma, R. Aldana, J. Clendenin, J. S Harris, R. F. W. Pease, IEEE Trans. Microwave Theory Tech. (to be published); Conference on Lasers and Electro-Optics, Baltimore MD, 1–6 June 2003]. The basic operating principle of the ADC is based on a miniaturized cathode ray tube where a bunch of photoemitted electrons passing through an electric deflection system is directed to a specific detector whence a digital code word emanates. The electron bunch samples the analog deflecting voltage that is then quantized according to the position of the detector receiving the bunch. The fundamental limit of the number of distinguishable voltage levels is the ratio of the deflecting voltage to the energy spread due to diffraction of the electron beam. This allows for up to 12bits at 100GS∕s [R. F. Pease, K. Ioakeimidi, R. Aldana, and R. Leheny, J. Vac. Sci. Technol. B 21, 2826 (2003)]. At a more practical level, the bit resolution is primarily limited by the uncertainty in the emission of each electron bunch (temporal jitter). For 100fs time uncertainty 5bits of resolution are attainable with the nitride cathode for a 50GHz bandwidth analog signal.

Photoelectronic analog-to-digital conversion using miniature electron optics: Basic design considerations

There is a continuing need for faster and more precise analog-to-digital converters (ADCs). State of the art ADCs have reached the 10 gigasamples/second (GS/s), 6–12 bit performance. We investigate an implementation of a 100 GS/s 4–6 bit ADC. The use of a cathode ray tube for analog-to-digital conversion was first described in the 1940s. The basic idea is that a bunch of electrons passing through an electric deflection system is directed to a specific detector whence a digital code word emanates. Thus the electron bunch samples the analog deflecting voltage which is then quantized according to the position of the detector receiving the bunch. The most fundamental limit to the number of distinguishable voltage levels is the ratio of the deflecting impulse to the momentum spread due to diffraction of the electron beam. This should allow up to 12 bits at 100 GS/s. At a more practical level the bit resolution and sampling frequency are limited by the brightness of the beam, the uncertainty in the time of emission of each bunch and by the maximum power needed to generate the analog voltage used to deflect the beam. For 50 V deflecting voltage and 100 fs timing uncertainty we should be able to achieve 4–5 bits for a 50 GHz bandwidth on the analog voltage (100 GS/s).

Detecting the Presence of Speech Using ADPCM Coding

When speech is coded using a differential pulse-code modulation system with an adaptive quantizer, the digital code words exhibit considerable variation among all quantization levels during both voiced and unvoiced speech intervals. However, because of limits on the range of step sizes, during silent intervals the code words vary only slightly among the smallest quantization steps. Based on this principle, a simple algorithm for locating the beginning and end of a speech utterance has been developed. This algorithm has been tested in computer simulations and has been constructed with standard integrated circuit technology.