Digital Cellular Applications Research Articles

1.2 V operation power heterojunction FET's for digital cellular applications

This paper describes 950 MHz power performance of 1.2 V drain bias operation n-AlGaAs/InGaAs/n-AlGaAs heterojunction FET's (HJFET) for personal digital cellular (PDC) applications. The fabricated HJFET with a 0.8-/spl mu/m long WSi gate exhibited an on-resistance (/spl tau//sub 0n/) of 2.1/spl Omega//spl middot/mm and a maximum drain current of 640 mA/mm. Operated at 1.2 V drain bias voltage, the HJFET with gate width of 28.0 mm demonstrated an output power of 30.0 dBm (1.0 W) and a power-added efficiency of 51.5% with an adjacent channel leakage power at 50 kHz off-center frequency of -50.8 dBc. Class A operation analysis, which shows a good coincidence with the measured PDC power performance, revealed that the excellent power performance with the relatively small gate width was due to the low /spl tau//sub 0n/ of the fabricated HJFET.

Double-doped power heterojunction FET for 1.5 V digital cellular applications

This article describes 1.5 V operation power performance of a double-doped AlGaAs/InGaAs/AlGaAs heterojunction FET (HJFET) for personal digital cellular phones. A 1.0 μm gate length HJFET exhibited 600 mA mm −1 maximum drain current, 260 mS mm −1 transconductance ( g m) and 9.4 V gate-to-drain breakdown voltage. Operated with a drain bias of 1.5 V, a 28 mm gate width HJFET demonstrated 1.02 W (30.1 dBm) output power and 45.2% power-added efficiency with −50.3 dBc adjacent channel leakage power at 50 kHz off-center frequency. This excellent power performance under 1.5 V operation was discussed with a low on-resistance of 2.5 ohm mm as well as with linear g m characteristics around an operating bias point.

High-linearity and small-chip AlGaAs/GaAs power HBTs for L-band personal digital cellular applications

A high-linearity AlGaAs/GaAs power heterojunction bipolar transistor (HBT) is developed for personal digital cellular phones. For compact chip layout, thermal design was considered. To improve power performance, proton implantation, optimum alloy condition for collector electrodes, and multiple via holes were used. A 2400-μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> -emitter-area HBT fabricated on a 0.5×0.67 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> substrate exhibits adjacent channel leakage powers below -53 dBc for 0.95- and 1.5-GHz /spl pi//4-shifted QPSK modulated input signals at a low collector-emitter voltage of 3.4 V. The HBT produces a 31.7-dBm output power, 50% power-added efficiency, and 15-dB linear power gain at 0.95 GHz, and produced a 31.3-dBm output power, 52% power-added efficiency, and 11.5-dB linear power gain at 1.5 GHz. These results were achieved on about one-fifth of the substrate area of conventional GaAs FETs.

Source second-harmonic control for high efficiency power amplifiers

A novel technology that drastically improves output power and efficiency of amplifiers has been developed, where source and load second-harmonic impedances, as well as the fundamental impedances, are optimally terminated in the input and output matching circuits. A record high 74% power-added efficiency (PAE) with 31.4 dBm (1.4 W) output power at a frequency of 930 MHz has been achieved as a single-stage saturated amplifier using an ion-implanted GaAs MESFET under the low supply voltage of 3.5 V. As a single-stage linear amplifier, an excellent PAE of 59% with 31.5 dBm output power has been realized at V/sub d/=4.7 V and f=948 MHz. Saturated and linear two-stage power modules operating at 900 MHz band with 31 dBm (1.25 W) output power have been demonstrated for analog and digital cellular applications respectively, the volume of which is as small as 0.4 cc. The saturated power module has achieved a PAE of 66% at V/sub d/=3.5 V, and the linear one has realized a PAE of 50% at V/sub d/=4.7 V.

Variable bit‐rate CELP coding of speech with phonetic classification

AbstractA variable bit‐rate speech coder intended for digital cellular applications is described. A voice activity detection algorithm is used to distinguish active speech from background noise. Each frame of active speech is further classified to distinguish between three phonetic categories: voiced, unvoiced, and onset. Each input frame is assigned one of five bit rates according to voice activity and phonetic classification and coded using an analysis‐by‐synthesis algorithm tailored to the needs of the class that it belongs to. The resulting coder, called Variable Rate Phonetic Segmentation, produces good quality speech at an average bit‐rate below 3 kbit/s when operating with a voice activity factor of 0.5. Informal subjective quality assessment for speech in clean and noisy backgrounds indicates a performance that is comparable to the TIA standard QCELP algorithm while operating at a 25% to 40% lower average bit rate.