Digital Arithmetic Research Articles

Exact Computing Multiplier Design using 5-to-3 Counters for Image Processing

This work presents a novel approach to improve the area and energy efficiency of 5:3 counter, a key element used in digital arithmetic. To provide an effective substitute for addition operations, mostly in the partial product reduction stage of larger multipliers, this study suggests a new 5:3 counter. The Input Shuffling Unit (ISU) is employed within the proposed 5:3 counter to minimize gate-level implementation and path delay during partial product reduction in 16-bit and larger multipliers, thereby enhancing area and energy efficiency. Consequently, there are 84% fewer choices of input-output combinations, thereby decreasing the circuit complexity with respect to area and energy usage. When compared to its existing counterparts, the suggested 5:3 compressor improves area utilization and energy usage by an average of 11%, 17%, and 17% in 8-, 16-, and 32-bit multipliers, respectively. The results of simulations demonstrate the superiority of our method over traditional designs, providing an increase in both area and energy efficiency. These results highlight the applicability and scalability of our method, which is appropriate for a variety of applications such as embedded systems and digital signal processing.

Multibeam Wideband Transmit Beamforming Using 2D Sparse FIR Trapezoidal Filters

A low-complexity multibeam wideband transmit beamformer using a 2D sparse FIR filter design capable of multiple beams is proposed as a digital building block for fully digital beamformers. The 2D sparse FIR filter has multiple trapezoid-shaped passbands pertaining to wideband beams aimed at particular directions. The proposed multibeam digital beamformer drives a uniform linear array of wideband antenna elements to achieve the wideband multibeam transmit-mode signals desired by the communication system. The 2D sparse FIR filter is designed to be optimal in the minimax sense using convex optimization techniques. Full-wave electromagnetic simulations using real antenna models confirm that the proposed wideband transmit beamformer can achieve multibeam transmission in the 1.3–2.8 GHz frequency range, with more than 70% fractional bandwidth. Furthermore, the adoption of the wideband transmit multibeam beamformer leads to a significant reduction in digital arithmetic (computational) complexity compared with previously reported wideband transmit beamformers of similar transfer function type, without deteriorating beam directionality and causing increases in the side-lobe level. The proposed sparse 2D FIR multibeam beamformer architecture is well-suited for both sub-6 GHz (legacy) band transmit beamforming, frequency range three (FR3) beamforming up to 28 GHz, and mmWave operation for emerging 5G/6G applications.

Analysis of Parallel Prefix Adders

Abstract: Parallel prefix adders are essential components of contemporary digital arithmetic circuits and are found in many different devices, including digital signal processors and microprocessors. In order to improve the effectiveness and performance of parallel prefix adders, this research investigates their design and optimization. This paper analyses in detail the state of the parallel prefix adder architectures and provide new designs that minimize power consumption and critical path delays. The speed and area efficiency benefits of the parallel prefix designs with thorough simulations and comparisons is reviewed. This research have ramifications for high-performance computing systems and point to interesting avenues to further the state of the art in parallel prefix adder design.

RETRACTED ARTICLE: A new design for 4-bit RCA using quantum cellular automata technology

Since the scaling of transistors is growing rapidly, the need for an efficient alternative for the Complementary Metal-Oxide-Semiconductor (CMOS) technology to obtain further and extra processes in the circuits has been known as the main problem. Over the last decade, Quantum-dot Cellular Automata (QCA) technology has been recognized as a suitable replacement for CMOS technology due to its excellent potential in developing designs with low-power consumption, high speed, and high density. In this regard, lowering the number of gates, the amount of cell count, and delay has been emphasized in the design of QCA-based circuits. As the main unit in logic circuits and digital arithmetic, adders play an important role in constructing various effective QCA designs. In this regard, Ripple Carry Adder (RCA) is a simple form of adders and, due to its remarkable features, can be useful to reach circuits with the minimum required area and power consumption. Therefore, this study recommends a new design for RCA in QCA technology to reduce the cell count, amend the complexity, and decrease the latency. To verify the correctness of the suggested circuit, the QCADesigner-E version 2.0.3 as a well-known simulator has been used. The evaluation results confirm that the proposed design has approximately 28.6% improvement in cell count compared to the state-of-the-art four-bit coplanar RCA designs in QCA technology. Also, the obtained results designate the effectiveness of the advised plan.

Design and Development of Digital Arithmetic Circuits Employing CMOS Technology for Performance Enhancement

Design and Development of Digital Arithmetic Circuits Employing CMOS Technology for Performance Enhancement

Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations

Parallelism is the key to enhancing the throughput of computing structures. However, it is well established that the presence of data-flow dependencies adversely impacts the exploitation of such parallelism. This paper presents a case for a new computing paradigm namely subscalar digital arithmetic which is aimed at mitigating this issue. It proposes to break up atomic data and atomic operations thereon into sub-atomic data fragments and sub-atomic partial operations. Such a break-up exposes hitherto unexploited levels of parallelism by way of allowing overlap of operations even if data-dependent. Surprisingly this enhanced exploitation of latent parallelism comes with a favorable impact on the area-power characteristics of corresponding computing structures which is contrary to common sense. The paper also proposes a novel micro cell library with logic primitives at corresponding subscalar levels. The synthesized circuits for several sequential benchmarks show an order of magnitude improvement in their area-throughput figure-of-merit (FOM).

A scalable high‐speed hybrid 1‐bit full adder design using XOR‐XNOR module

AbstractHigh‐speed XOR‐XNOR‐based hybrid full adder (FA) using a combination of three logic techniques (transmission gate [TG], conventional CMOS [CCMOS], pass transistor [PT]) is presented in this work. Performance analysis and validation of the FA design presented in this work have been realized with reference to 10 state‐of‐the‐art FAs. The scalability of the design has been tested by extending FA up to 32‐bits in ripple carry adder (RCA) style. It has been observed that only four existing FAs and the proposed FA could be scaled up to 32‐bits without including voltage restoration buffers in the internal stages. The proposed XOR‐XNOR‐based FA showed excellent performance metrics, both as a 1‐bit adder cell as well as in wide word length adder form. Hence, the proposed XOR‐XNOR‐based hybrid FA can serve as a better alternative to the existing FAs in digital arithmetic blocks of modern microprocessors.

Digital Error Correction Logic for Pipelined ADC Using 1.5Bits/Stage

Low power, high resolution and high-speed ADCs are becoming increasingly important with advancements in portable electronics, from mobile phones and pagers to CD players and MP3 players. This is certainly not feasible on a handheld device which is why new ADC techniques must be developed. They are becoming increasingly attractive to major data converter manufacturers and their designers because pipeline ADCs provide an optimal balance of scale, speed, resolution, power dissipation and analogue design effort. Because of latency and errors in comparators & gain stages in pipelined ADCs, the need arises for digital error correction mechanism. The digital error correction logic will be implemented for 8-bit ADC using 1.5 bits per stage. While designing we are considering important parameters of CMOS like propagation delay performance and power dissipation. The VLSI realization of digital arithmetic is implemented using TANNER EDA software tool using 0.18µm CMOS process.

Computing with logarithmic number system arithmetic: Implementation methods and performance benefits

The logarithmic number system (LNS) has found appeal in digital arithmetic because it allows multiplication and division to be performed much faster and more accurately than with widely-used floating-point (FP) number formats. We present a comprehensive review and comparison of various techniques and architectures for performing arithmetic operations efficiently in LNS, using the sign/logarithm format, and focus on the European Logarithmic Microprocessor (ELM), a device built in the framework of a research project launched in 1999, as an important case study. Comparison of the arithmetic performance of ELM with that of a commercial superscalar pipelined FP processor of the same vintage and technology confirms that LNS has the potential for successful deployment in general-purpose systems. Besides paying due attention to LNS attributes beyond computational speed and accuracy, novel contributions of this survey include an exploration of the relationship of LNS with the emerging field of approximate computing and a discussion of the discrete logarithmic number system.

The Effectiveness of Android Based Digital Arithmetic Learning Media with Discovery-Based Learning Model to the Learning Achievement of Computer System Subject of Grade X of Multimedia Class at Vocational High School in Surakarta

<p>The purpose of this research is to determine (1) the effectiveness of the use of learning media based on android Arithmetic Digital with discovery-based learning model to learning achievement of computer system grade X of multimedia class at vocational high school 6 Surakarta, (2) the differences in students’ achievement between the control class and experimental class were given the action of using Android learning media with discovery-based learning model. The population of this research is students of grade X of Multimedia class at Vocational high school 6 Surakarta. This study uses an experimental quasi-approach. The techniques of data collection in this study using the test method to determine the results of pretest and post-test. The observation method is to know the difference of student activity of control class and experiment class. Data analysis used was non-parametric test by using Mann Whitney test and Wilcoxon rank test.</p><p>Based on the research, it can be concluded that the Android-based learning media with discovery-based learning model more effective in improving learning achievement compared with the conventional model. This is evidenced by the Wilcoxon sign rank test which gives a result of the significance of 0.000 < 0.005, which means there is a difference in mean values between the two classes. The experimental class got a higher average score that is 84.14 and the control class is 67.59. The result of this research is also reinforced by student gain index analysis, with gain of experimental class that is 0,70 which mean inclination category of high learning achievement while the gain’s improvement of control class is equal to 0,40 which means inclusive category of improvement in learning achievement, this matter because in the model of discovery-based learning able to improve student activeness in learning as well as to develop student's way of learning by finding their own, and self-investigate. And combined with the right learning media such as Android, will increasingly foster student interest in learning.</p>

Shannon Logic Based Novel QCA Full Adder Design with Energy Dissipation Analysis

Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology to replace VLSI-CMOS digital circuits. Due to its attractive features such as low power consumption, ultra-high speed switching, high device density, several digital arithmetic circuits have been proposed. Adder circuit is the most prominent component used for arithmetic operations. All other arithmetic operation can be successively performed using adder circuits. This paper presents Shannon logic based QCA efficient full adder circuit for arithmetic operations. Shannon logic expression with control variables helps the designer to reduce hardware cost; using with minimum foot prints of the chip size. The mathematical models of the proposed adder are verified with the theoretical values. In addition, the energy dissipation losses of the proposed adder are carried out. The energy dissipation calculation is evaluated under the three separate tunneling energy levels, at temperature T = 2K.The proposed adder dissipates less power. QCAPro tool is used for estimating the energy dissipation. In this paper we proposed novel Shannon based adder for arithmetic calculations. This adder has been verified in different aspects like using Boolean algebra besides it power analysis has been calculated. In addition 1-bit full adder has been enhanced to propose 2-bit and 4-bit adder circuits.

ISAAC

A number of recent efforts have attempted to design accelerators for popular machine learning algorithms, such as those involving convolutional and deep neural networks (CNNs and DNNs). These algorithms typically involve a large number of multiply-accumulate (dot-product) operations. A recent project, DaDianNao, adopts a near data processing approach, where a specialized neural functional unit performs all the digital arithmetic operations and receives input weights from adjacent eDRAM banks. This work explores an in-situ processing approach, where memristor crossbar arrays not only store input weights, but are also used to perform dot-product operations in an analog manner. While the use of crossbar memory as an analog dot-product engine is well known, no prior work has designed or characterized a full-fledged accelerator based on crossbars. In particular, our work makes the following contributions: (i) We design a pipelined architecture, with some crossbars dedicated for each neural network layer, and eDRAM buffers that aggregate data between pipeline stages. (ii) We define new data encoding techniques that are amenable to analog computations and that can reduce the high overheads of analog-to-digital conversion (ADC). (iii) We define the many supporting digital components required in an analog CNN accelerator and carry out a design space exploration to identify the best balance of memristor storage/compute, ADCs, and eDRAM storage on a chip. On a suite of CNN and DNN workloads, the proposed ISAAC architecture yields improvements of 14.8×, 5.5×, and 7.5× in throughput, energy, and computational density (respectively), relative to the state-of-the-art DaDianNao architecture.

An efficient design of full adder in quantum-dot cellular automata (QCA) technology

The full adder circuit is a basic unit in digital arithmetic and logic circuits. In this paper an improved full adder in QCA technology is proposed. This design is considerably declined in terms of cell numbers and area, compared to other full adders and delay is kept at minimum. To design this full adder a different formulation for sum and carry outputs of full adder has been used. The simulation results in QCADesigner software confirm that the presented circuit works well and can be used as a high performance design in QCA technology. Finally, the proposed QCA full adder is used to make three sizes of ripple carry adders (RCA) and acceptable results are achieved.

Systolic array architecture for steerable multibeam VHF wave-digital RF apertures

A 2-D massively parallel, high throughput, systolic array for a spatio-temporal wave-digital filter (WDF) architecture is proposed. RF receive mode aperture beam personalities are achieved using 2-D fan filters with dynamically steerable passband directions and fan angles. The wave-digital realization results in low sensitivity of the far-field beam to errors in filter coefficients due to fixed-point effects in the digital arithmetic hardware. A fixed-point design of the systolic-array architecture that eliminates overflow errors is described. The architecture is implemented in FPGA-prototype form and tested using MATLAB Simulink with Xilinx EDA tools. The verified digital design is ported to CMOS standard-cell technology to obtain the area and power costs as well as the operational frequency. The 45 nm CMOS synthesis, placement, and routing show overflow free maximum frequency of operation of 131.02 MHz for 1-passband fan filter and an estimated power consumption of 450.30 mW at DC supply voltage 1.1 V indicating potential applications in the VHF range.

Digital Arithmetic in Nature: Continuous-Digit RNS

© The British Computer Society 2014. It has been reported in the literature on computational neuroscience that a rat's uncanny ability to dash back to a home position in the absence of any visual clues (or in total darkness, for that matter) may stem from its distinctive method of position representation. More specifically, it is hypothesized that the rat uses a multimodular method akin to residue number system (RNS), but with continuous residues or digits, to encode position information. After a brief review of the evidence in support of this hypothesis, and how it relates to RNS, we discuss the properties of continuous-digit RNS, and derive results on the dynamic range, representational accuracy and factors affecting the choice of the moduli, which are themselves real numbers. We conclude with suggestions for further research on important open problems concerning the process of selection, or evolutionary refinement, of the set of moduli in such a representation.

A Modified Approach to Low Power Digital Modeling of Recursive Filters For Analog Signal

The focus of this paper is towards developing an application specific design methodology for low power solutions in recursive coding system in which filtration process is performed by using MAC approach. For the realization of this MAC operation a recursive multiplication and addition operation is carried out. Theconventional recursion results in multiple accumulation operation in successive clocks of duration amounting to that of an addition-time, so that the accumulation of �� successive input words are performed in ��clock cycles. For large values of ��, a computational latency of ��addition-time over head and high power consumption and accumulation process to obtain an accumulated output could be too high to meet the timing requirement in real-time application. so in order to over this problem in this paper a new scalable Repetitive multiply accumulates (MACs) is proposed.From the simulation results the proposed MAC has less delay complexity and low power consumption when compared to the conventional approaches. Keyword: Recursive coding, VLSI, Application specific integrated circuits, digital signal processing chips , digital arithmetic.

Hardware Implementation of A High Speed Inverse Park Transformation Using CORDIC and PLL for FOC Brushless Servo Drive

Field Oriented Control in Permanent Magnet Synchronous Motor needs a quick computation in extremely short time to get an optimal efficiency and stability of the motor. The aim of this research is to present a fully integrated solution of inverse Park transformation by incorporating Coordinate Rotation Digital Computer, ARITHMETIC and Phase-locked Loop (PLL) module. But, the main problem in presenting such solution lies in completing the transformation within a limited clock cycles to pledge the steadiness of the motor where presently is the main issues of this industry. This research presents a transformation that works within 4 clock cycles with an execution time of 160ns of 24MHz frequency with an accuracy of 99.9 % which is the lowest computational cycle for the era.

Implemention of FIR Filter Based on DSP

DSP chip is especially fit for digital signal processing. Its main application is realizing all kinds of digital signal processing arithmetic such as clove hitch correlation, all kinds of transforms etc. Realizing digital filters with DSP is an important application. The paper discusses the filter’s software realization based on TMS320C5410 and finished the hardware systems of noise-restraining.The main works accomplished are as following: realization of FIR filter with window function, and realization on TMS320C5410 chip, the result of experiment to make clear.

BLOCK-PARALLEL SYSTOLIC-ARRAY ARCHITECTURE FOR 2-D NTT-BASED FRAGILE WATERMARK EMBEDDING

Number-theoretic transforms (NTTs) have been applied in the fragile watermarking of digital images. A block-parallel systolic-array architecture is proposed for watermarking based on the 2-D special Hartley NTT (HNTT). The proposed core employs two 2-D special HNTT hardware cores, each using digital arithmetic over GF(3), and processes 4 × 4 blocks of pixels in parallel every clock cycle. Prototypes are operational on a Xilinx Sx35-10ff668 FPGA device. The maximum estimated throughput of the FPGA circuit is 100 million 4 × 4 HNTT fragile watermarked blocks per second, when clocked at 100 MHz. Potential applications exist in high-traffic back-end servers dealing with large amounts of protected digital images requiring authentication, in remote-sensing for high-security surveillance applications, in real-time video processing of information of a sensitive nature or matters of national security, in video/photographic content management of corporate clients, in authenticating multimedia for the entertainment industry, in the authentication of electronic evidence material, and in real-time news streaming.

Digital Architectures for UWB Beamforming Using 2D IIR Spatio-Temporal Frequency-Planar Filters

A design method and an FPGA-based prototype implementation of massively parallel systolic-array VLSI architectures for 2nd-order and 3rd-order frequency-planar beam plane-wave filters are proposed. Frequency-planar beamforming enables highly-directional UWB RF beams at low computational complexity compared to digital phased-array feed techniques. The array factors of the proposed realizations are simulated and both high-directional selectivity and UWB performance are demonstrated. The proposed architectures operate using 2's complement finite precision digital arithmetic. The real-time throughput is maximized using look-ahead optimization applied locally to each processor in the proposed massively-parallel realization of the filter. From sensitivity theory, it is shown that 15 and 19-bit precision for filter coefficients results in better than 3% error for 2nd- and 3rd-order beam filters. Folding together with Ktimes multiplexing is applied to the proposed beam architectures such that throughput can be traded forK-fold lower complexity for realizing the 2-D fan filter banks. Prototype FPGA circuit implementations of these filters are proposed using a Virtex 6 xc6vsx475t-2ff1759 device. The FPGA-prototyped architectures are evaluated using area (A), critical path delay (T), and metricsATandAT2. TheL2error energy is used as a metric for evaluating fixed-point noise levels and the accuracy of the finite precision digital arithmetic circuits.