Digit-serial Multiplier Research Articles

Input–Output Scheduling and Control for Efficient FPGA Realization of Digit-Serial Multiplication Over Generic Binary Extension Fields

Input–Output Scheduling and Control for Efficient FPGA Realization of Digit-Serial Multiplication Over Generic Binary Extension Fields

Power/Area-Efficient ECC Processor Implementation for Resource-Constrained Devices

The use of resource-constrained devices is rising nowadays, and these devices mostly operate with sensitive data. Consequently, security is a key issue for these devices. In this paper, we propose a compact ECC (elliptic curve cryptography) architecture for resource-constrained devices based on López–Dahab (LD) projective point arithmetic operations on GF(2m). To achieve an efficient area-power hardware ECC implementation, an efficient digit-serial multiplier is developed. The proposed multiplier is built on a Bivariate Polynomial Basis representation and a modified Radix-n Interleaved Multiplication (mRnIM) method (for area and power complexities reduction). Furthermore, the LD-Montgomery point multiplication algorithm is adjusted for accurate scheduling in the compact ECC architecture to eliminate data reliance and improve signal management. Meanwhile, the area complexity is reduced by reuse of resources, and clock gating and asynchronous counter are exploited to reduce the power consumption. Finally, the proposed compact ECC architecture is implemented over GF(2m) (m = 163, 233, 283, 409, and 571) on Xilinx FPGAs’ (Field-Programmable Gate Array) Virtex 5, Virtex 6, and Virtex 7, showing that the efficiency of this design outperforms to date when compared to reported works individually. It utilizes less area and consumes low power. The FPGA results clearly demonstrate that the proposed ECC architecture is appropriate for constraint-resources devices.

Efficient implementation of digit‐serial Montgomery modular multiplier architecture

The importance of security in communications has made cryptography one of the most important research for designers. Montgomery modular multiplication is one of the best methods used in cryptosystems. These multipliers can be implemented in different ways including digit-serial architecture. The digit-serial multiplier is an efficient structure for low power and high-speed applications. The architecture of digit-serial multiplier can benefit from the advantage of both serial and parallel structures. This study presents a new digit-serial Montgomery modular multiplier architecture, which takes up less area by reducing internal blocks of the structure. The latency and design complexity of the proposed digit-serial Montgomery multiplier is less than many other similar designs. The critical path delay of the proposed architecture is reduced compared to similar works. The proposed circuit has the flexibility to be used in a large number of bits and can be used for any size of the digit. The simulation results of the proposed multiplier are presented.

Design of a digit-serial multiplier over GF(2m) using a karatsuba algorithm

ABSTRACTA Karatsuba algorithm (KA) is used for highly accurate multiplication using a divide and conquer approach. A new approach to a polynomial digit-serial multiplier that uses an optimal digit size (d) for KA decomposition has recently been proposed. In this study, the proposed architecture uses three small multipliers to derive an optimal digit size (d) for the case of trinomial based fields. Using the proposed KA decomposition, this study establishes five types of sub-quadratic multipliers, which are, the recombined m-bit exponentiation multipliers using a KA. The theoretical results show that the proposed polynomial exponentiation multipliers that use a KA have a value of (d × m)/2 and involve significantly less time and area complexity than existing digit-serial multipliers. The simulation results for the proposed method demonstrate a respective 68.20%, 77.37%, 72%, 83.18%, 36.66% decrease in area × time over GF(236), GF(284), GF(2126), GF(2204) and GF(2340).

Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix–Vector Product Approach

Systolic finite field multiplier over $GF(2^{m})$ , because of its superior features such as high throughput and regularity, is highly desirable for many demanding cryptosystems. On the other side, however, obtaining high-performance systolic multiplier with relatively low hardware cost is still a challenging task due to the fact that the systolic structure usually involves large area complexity. Based on this consideration, in this paper, we propose to carry out two novel coherent interdependent efforts. First, a new digit-serial multiplication algorithm based on polynomial basis over binary field $(GF(2^{m}))$ is proposed. Novel Toeplitz matrix–vector product (TMVP)-based decomposition strategy is employed to derive an efficient subquadratic space complexity. Second, The proposed algorithm is then innovatively mapped into a low-complexity systolic multiplier, which involves less area-time complexities than the existing ones. A series of resource optimization techniques also has been applied on the multiplier which optimizes further the proposed design (it is the first report on digit-serial systolic multiplier based on TMVP approach covering all irreducible polynomials, to the best of our knowledge). The following complexity analysis and comparison confirm the efficiency of the proposed multiplier, that is, it has lower area-delay product (ADP) than the existing ones. The extension of the proposed multiplier for bit-parallel implementation is also considered in this paper.

Digit-Serial Versatile Multiplier Based on a Novel Block Recombination of the Modified Overlap-Free Karatsuba Algorithm

Overlap-Free Karatsuba Algorithm (OFKA) combined with block recombination approach (OFKABR) can improve the complexity of the original OFKA to obtain efficient implementation of polynomial basis multiplication over finite field $GF(2^{m})$ . In this paper, we have further proposed a modified OFKABR (MOFKABR) strategy to reduce the space and time complexities of the best-known method. The proposed strategy is also extended to obtain a low-complexity versatile multiplier, which is designed to support the generalized multiplication on a wider range of field size for $m_{1}\leq m\leq m_{\lambda }$ . Using the proposed MOFKABR approach, the proposed digit-serial versatile multiplier can achieve subquadratic space complexity when compared with the existing digit-serial versatile multipliers.

Novel Hybrid-Size Digit-Serial Systolic Multiplier over GF(2m)

Because of the efficient tradeoff in area–time complexities, digit-serial systolic multiplier over G F ( 2 m ) has gained substantial attention in the research community for possible application in current/emerging cryptosystems. In general, this type of multiplier is designed to be applicable to one certain field-size, which in fact determines the actual security level of the cryptosystem and thus limits the flexibility of the operation of cryptographic applications. Based on this consideration, in this paper, we propose a novel hybrid-size digit-serial systolic multiplier which not only offers flexibility to operate in either pentanomial- or trinomial-based multiplications, but also has low-complexity implementation performance. Overall, we have made two interdependent efforts to carry out the proposed work. First, a novel algorithm is derived to formulate the mathematical idea of the hybrid-size realization. Then, a novel digit-serial structure is obtained after efficient mapping from the proposed algorithm. Finally, the complexity analysis and comparison are given to demonstrate the efficiency of the proposed multiplier, e.g., the proposed one has less area-delay product (ADP) than the best existing trinomial-based design. The proposed multiplier can be used as a standard intellectual property (IP) core in many cryptographic applications for flexible operation.

Low Register-Complexity Systolic Digit-Serial Multiplier Over Based on Trinomials

Digit-serial systolic multipliers over $GF(2^m)$ based on the National Institute of Standards and Technology (NIST) recommended trinomials play a critical role in the real-time operations of cryptosystems. Systolic multipliers over $GF(2^m)$ involve a large number of registers of size $O(m^2)$ which results in significant increase in area complexity. In this paper, we propose a novel low register-complexity digit-serial trinomial-based finite field multiplier. The proposed architecture is derived through two novel coherent interdependent stages: (i) derivation of an efficient hardware-oriented algorithm based on a novel input-operand feeding scheme and (ii) appropriate design of novel low register-complexity systolic structure based on the proposed algorithm. The extension of the proposed design to Karatsuba algorithm (KA)-based structure is also presented. The proposed design is synthesized for FPGA implementation and it is shown that it (the design based on regular multiplication process) could achieve more than 12.1 percent saving in area-delay product and nearly 2.8 percent saving in power-delay product. To the best of the authors’ knowledge, the register-complexity of proposed structure is so far the least among the competing designs for trinomial based systolic multipliers (for the same type of multiplication algorithm).

Efficient Implementation of Karatsuba Algorithm Based Three-Operand Multiplication Over Binary Extension Field

Three-operation multiplication (TOM) over binary extension field is frequently encountered in cryptosystems such as elliptic curve cryptography. Though digit-serial polynomial basis multipliers are usually preferred for the realization of TOM due to their efficient tradeoff in implementation complexity, the Karatsuba algorithm (KA)-based strategy is rarely employed to reduce the complexity further. Based on this reason, in this paper, we derive a novel low-complexity implementation of TOM based on a new KA-based digit-serial multiplier. The proposed TOM is obtained through two novel coherent interdependent efforts: 1) mapping an efficient KA-based algorithm into a novel digit-serial multiplier and 2) obtaining a new TOM structure through the novel derivation of the TOM algorithm. From the estimated results, it is shown that the proposed structure has significant lower area-time-complexities when compared with the existing competing TOMs. The proposed TOM is highly regular with low-complexity, and hence can be employed in many cryptographic applications.

Low‐latency digit‐serial dual basis multiplier for lightweight cryptosystems

Various cryptosystems, such as elliptic curve and pairing-based cryptosystems, in resource-constrained security applications rely on finite field multiplication. For applications such as these, a digit-serial multiplier has the potential features to achieve a trade-off between space and time complexities. The authors propose an efficient decomposition of the multiplication into four independent sub-multiplication units to facilitate parallel processing, which is additionally facilitated by the systolic structures of the sub-multiplication units. The proposed architecture uses a four-bit scheme to construct a novel processing element, instead of using only one bit as is currently used in similar multipliers. The results of the synthesis show that the proposed digit-serial dual basis multiplier eliminates up to 96% of the critical path delay.

Efficient FPGA Implementation of Low-Complexity Systolic Karatsuba Multiplier Over $GF(2^{m})$ Based on NIST Polynomials

Systolic implementation of Karatsuba algo- rithm (KA)-based digit-serial multiplier over $GF(2^{m})$ on field- programmable gate array (FPGA) platforms has many attractive features, such as efficient tradeoff in area-time complexity and high-throughput rate. But on the other side, it suffers from high register-complexity, which leads to increase in area and power consumption. In this paper, we present an algorithm and architecture for efficient FPGA implementation of KA-based digit-serial systolic multiplier over $GF(2^{m})$ based on the National Institute of Standards and Technology (NIST) recommended polynomials. A number of efficient techniques have been explored and used to realize efficient implementation of these multipliers. First, we propose a novel KA-based approach, where the computational complexity is significantly reduced compared with the existing one. Second, we propose efficient register minimization techniques, such as redundant register removal, two-stage pipelining, and register sharing to reduce the register complexity of the proposed structure. Third, we adopt an efficient FPGA-specific digit-parallel implementation strategy to optimize the area-time–power complexities of the proposed structure on FPGA platforms. The results obtained from FPGA synthesis indicate that the proposed multiplier (for field based on NIST trinomial $GF(2^{233})$ ) has significantly lower area–time–power complexities than the existing designs, e.g., the proposed structure could achieve 65.7% and 73.6% reduction on area-delay product and power-delay product over the best of existing KA-based systolic structures, respectively.

VLSI Implementation of Low Power High Speed ECC Processor Using Versatile Bit Serial Multiplier

In this paper, an area competent field-programmable gate array (FPGA) execution scheme of elliptic curve cryptography (ECC) is depicted. There are numerous limitations in traditional encryption algorithms such us Rivest Shamir Adleman (RSA), Advanced Encryption Standard (AES) in respect of security, power, and resources at the real-time performance. The ECC is mounting as an imperative cryptography, and gives you an idea about a promise to be the substitute of RSA. In this paper, ECC processor architecture over Galois Fields (GFs) with the multitalented bit serial multiplier is depicted which accomplishes the greatest area and power performance over traditional digit-serial multiplier. In addition, the vigilant scheduling operation was employed to diminish the involvedness of logic unit operations in ECC processor. The anticipated architecture is executed on vertex4 FPGA expertise in Xilinx software. We demonstrate that results perk up the performance of the enhanced design by contrasting with the traditional design.

Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique

In CMOS-based application-specific integrated circuit (ASIC) designs, total power consumption is dominated by dynamic power, where dynamic power consists of two major components, namely, switching power and internal power. In this paper, we present a low-power design for a digit-serial finite field multiplier in GF $(2^{m})$ . In the proposed design, a factoring technique is used to minimize switching power. To the best of our knowledge, factoring method has not been reported in the literature being used in the design of a finite field multiplier at an architectural level. Logic gate substitution is also utilized to reduce internal power. Our proposed design along $\vphantom {_{A}}$ with several existing similar works have been realized for GF $(2^{233})$ on ASIC platform, and a comparison is made between them. The synthesis results show that the proposed multiplier design consumes at least 27.8% lower total power than any previous work in comparison.

Low-Complexity Digit-Serial Multiplier Over $GF(2^{m})$ Based on Efficient Toeplitz Block Toeplitz Matrix–Vector Product Decomposition

In this paper, we have shown that a regular Toeplitz matrix-vector product (TMVP) can be transformed into a Toeplitz block TMVP (TBTMVP) using a suitable permutation matrix. Based on the TBTMVP representation, we have proposed a new $(a,b)$ -way TBTMVP decomposition algorithm for implementing a digit-serial multiplication. Moreover, it is shown that, based on iterative block recombination, we can improve the space complexity of the proposed TBTMVP decomposition. From the synthesis results, we have shown that the proposed TBTMVP-based multiplier involves less area, less area-delay product, and higher throughput compared with the existing digit-serial multipliers.

Efficient digit serial architecture for sign based least mean square adaptive filter for denoising of artefacts in ECG signals

Variants of Least Mean Square algorithm, namely the Sign Error, Sign Regressor and Sign-Sign Least Mean Square algorithms are meant for reducing computational complexity in digital adaptive filters in denoising electrocardiogram signals. In adaptive filtering using Sign-Sign algorithm, the adders and multipliers in the existing method take the coefficients in canonic signed power of two form which assures that between two non-zero there should be one zero in signed power of two digits and they can process only one bit per clock cycle and so is the filter resulting in low speed. In this paper, digit serial adder and digit serial multiplier are proposed to design the Sign-Sign Least Mean Square filter, which increases the speed by processing two bits per clock cycle. The digit serial adder and digit serial multiplier are used to design the Sign-Sign based adaptive filter in which unfolding technique is used for digit serial realisation. The unfolding factor of K = 2 is chosen to increase the speed of the design. The coefficients and its inputs are represented in Canonic Signed Digit form. Adder, multiplier, adaptive filter of both existing and proposed method are simulated using Mentor Graphics and synthesised using Synopsys Design Compiler Tool with 90 nm technology. From the results it is observed that the speed of the proposed digit serial Sign-Sign Least Mean Square filter is increased by 54.5% and the area of the filter is decreased by 4.21% compared to the bit serial Sign-Sign Least Mean Square filter.

Efficient digit serial architecture for sign based least mean square adaptive filter for denoising of artefacts in ECG signals

Variants of Least Mean Square algorithm, namely the Sign Error, Sign Regressor and Sign-Sign Least Mean Square algorithms are meant for reducing computational complexity in digital adaptive filters in denoising electrocardiogram signals. In adaptive filtering using Sign-Sign algorithm, the adders and multipliers in the existing method take the coefficients in canonic signed power of two form which assures that between two non-zero there should be one zero in signed power of two digits and they can process only one bit per clock cycle and so is the filter resulting in low speed. In this paper, digit serial adder and digit serial multiplier are proposed to design the Sign-Sign Least Mean Square filter, which increases the speed by processing two bits per clock cycle. The digit serial adder and digit serial multiplier are used to design the Sign-Sign based adaptive filter in which unfolding technique is used for digit serial realisation. The unfolding factor of K = 2 is chosen to increase the speed of the design. The coefficients and its inputs are represented in Canonic Signed Digit form. Adder, multiplier, adaptive filter of both existing and proposed method are simulated using Mentor Graphics and synthesised using Synopsys Design Compiler Tool with 90 nm technology. From the results it is observed that the speed of the proposed digit serial Sign-Sign Least Mean Square filter is increased by 54.5% and the area of the filter is decreased by 4.21% compared to the bit serial Sign-Sign Least Mean Square filter.

Low Complexity Digit Serial Multiplier for Finite Field using Redundant Basis

Cryptography has been increasingly used due to its rapid trends. In recent days, it has been used mostly in communication and in financial transactions through automated machines or internet. The applications of cryptography and coding theory require finite field operations and are realized based on the finite field computations. In this paper efficient digit-serial multiplier over finite field is implemented and is obtained by using Redundant Basis (RB), intend to present highthroughput multiplier. Area and power are the two factors which obtain less when compared to the previous multipliers. The digit-serial multiplier for 32-bit is implemented using Verilog HDL and synthesized to know its better performance in terms of area and power compared to previous multipliers.

Comment on “Subquadratic Space-Complexity Digit-Serial Multipliers Over <inline-formula> <tex-math notation="LaTeX">$GF(2^{m})$</tex-math> </inline-formula> Using Generalized <inline-formula> <tex-math notation="LaTeX">$(a, b)$</tex-math> </inline-formula>-Way Karatsuba Algorithm”

In the literature, the generalized $(a, b)$ - way Karatsuba algorithm (KA) is a well-known high-precision technique for implementing a subquadratic digit-serial multiplication. We present here the corrections to the space and complexities pertaining to addition operations in $(a, b)$ -way KA approach.

Area-Delay Efficient Digit-Serial Multiplier Based on <inline-formula> <tex-math notation="LaTeX">$k$ </tex-math> </inline-formula>-Partitioning Scheme Combined With TMVP Block Recombination Approach

Shifted polynomial basis (SPB) and generalized polynomial basis (GPB) are two efficient bases of representation in binary extension fields, and are widely studied. In this paper, we use the GPB formulation to derive a new modified SPB (MSPB) representation for arbitrary irreducible trinomials and pentanomials. It is shown that the basis conversion from the MSPB to the SPB for trinomials is free of hardware cost. We have shown that multiplication based on SPB and MSPB representations can make use of Toeplitz matrix–vector product (TMVP) formulation. The existing TMVP block recombination (TMVPBR) approach is used here to derive an efficient $k$ -partitioning TMVPBR decomposition for digit-serial double basis multiplication that can achieve subquadratic space complexity. From synthesis results, we have shown that the proposed multiplier has less area and less area-delay product compared with the existing digit-serial multipliers. We also show that the proposed multiplier using $k$ -partitioning TMVPBR decomposition can provide a better tradeoff between time and space complexities.

Throughput/Area-efficient ECC Processor Using Montgomery Point Multiplication on FPGA

High throughput while maintaining low resource is a key issue for elliptic curve cryptography (ECC) hardware implementations in many applications. In this brief, an ECC processor architecture over Galois fields is presented, which achieves the best reported throughput/area performance on field-programmable gate array (FPGA) to date. A novel segmented pipelining digit serial multiplier is developed to speed up ECC point multiplication. To achieve low latency, a new combined algorithm is developed for point addition and point doubling with careful scheduling. A compact and flexible distributed-RAM-based memory unit design is developed to increase speed while keeping area low. Further optimizations were made via timing constraints and logic level modifications at the implementation level. The proposed architecture is implemented on Virtex4 (V4), Virtex5 (V5), and Virtex7 (V7) FPGA technologies and, respectively, achieved throughout/slice figures of 19.65, 65.30, and 64.48 $(10^{6}/ (\mbox{Seconds} \times \mbox{Slices}))$ .