Digit-serial Adder Research Articles

Self-Timed Adaptive Digit-Serial Addition

A fundamental operator in modern computational systems has a multitude of highly optimized implementations. In general-purpose systems, the width has grown to 128 bits, putting pressure on designers to use sophisticated carry lookahead or tree adders to maintain throughput while sacrificing area and energy. However, the typical workload mostly exercises the lower 10–15 bits. This leaves many devices on and unused during normal operation, reducing the overall performance. We hypothesize that bit- or digit-serial implementations for arbitrary-length streams represent an opportunity to decrease the overall energy usage while increasing the throughput/area efficiency of the system and verify this hypothesis by constructing an asynchronous digit-serial adder for comparison against its bit-parallel counterparts.

Efficient digit serial architecture for sign based least mean square adaptive filter for denoising of artefacts in ECG signals

Variants of Least Mean Square algorithm, namely the Sign Error, Sign Regressor and Sign-Sign Least Mean Square algorithms are meant for reducing computational complexity in digital adaptive filters in denoising electrocardiogram signals. In adaptive filtering using Sign-Sign algorithm, the adders and multipliers in the existing method take the coefficients in canonic signed power of two form which assures that between two non-zero there should be one zero in signed power of two digits and they can process only one bit per clock cycle and so is the filter resulting in low speed. In this paper, digit serial adder and digit serial multiplier are proposed to design the Sign-Sign Least Mean Square filter, which increases the speed by processing two bits per clock cycle. The digit serial adder and digit serial multiplier are used to design the Sign-Sign based adaptive filter in which unfolding technique is used for digit serial realisation. The unfolding factor of K = 2 is chosen to increase the speed of the design. The coefficients and its inputs are represented in Canonic Signed Digit form. Adder, multiplier, adaptive filter of both existing and proposed method are simulated using Mentor Graphics and synthesised using Synopsys Design Compiler Tool with 90 nm technology. From the results it is observed that the speed of the proposed digit serial Sign-Sign Least Mean Square filter is increased by 54.5% and the area of the filter is decreased by 4.21% compared to the bit serial Sign-Sign Least Mean Square filter.

Efficient digit serial architecture for sign based least mean square adaptive filter for denoising of artefacts in ECG signals

Variants of Least Mean Square algorithm, namely the Sign Error, Sign Regressor and Sign-Sign Least Mean Square algorithms are meant for reducing computational complexity in digital adaptive filters in denoising electrocardiogram signals. In adaptive filtering using Sign-Sign algorithm, the adders and multipliers in the existing method take the coefficients in canonic signed power of two form which assures that between two non-zero there should be one zero in signed power of two digits and they can process only one bit per clock cycle and so is the filter resulting in low speed. In this paper, digit serial adder and digit serial multiplier are proposed to design the Sign-Sign Least Mean Square filter, which increases the speed by processing two bits per clock cycle. The digit serial adder and digit serial multiplier are used to design the Sign-Sign based adaptive filter in which unfolding technique is used for digit serial realisation. The unfolding factor of K = 2 is chosen to increase the speed of the design. The coefficients and its inputs are represented in Canonic Signed Digit form. Adder, multiplier, adaptive filter of both existing and proposed method are simulated using Mentor Graphics and synthesised using Synopsys Design Compiler Tool with 90 nm technology. From the results it is observed that the speed of the proposed digit serial Sign-Sign Least Mean Square filter is increased by 54.5% and the area of the filter is decreased by 4.21% compared to the bit serial Sign-Sign Least Mean Square filter.

Design of fast digit-serial adders using SFQ logic circuits

We propose an algorithm of digit-serial adders using single-flux-quantum (SFQ) circuits. The proposed digit-serial adder adapts the carry look-ahead (CLA) adder architecture to generate carry signals, which are generated from the digit-serial data and fed back internally to the following digit-serial data to increase the throughput of the calculation. We have designed and implemented a 4-bit digit-serial adder using the SRL 2.5kA/cm2 niobium standard process to demonstrate its high-speed operation. The total number of Josephson junctions is 2316. We have successfully tested full operations of the 4-bit digit-serial adder with a bias margin of ± 15% at 25GHz. Its maximum operation frequency was 30GHz.

Design of a square-root architecture: digit-serial approach

Abstract A new digit-serial square-root architecture based on radix-2n arithmetic is presented. First, the conventional binary square-root algorithm is modified to a digit-serial algorithm which is used to design the proposed architecture. This architecture consists of a number of/i-bit controlled add/subtract (CAS) cells. We present two CAS cell architectures. The first is based on the conventional carry feed-back digit serial adder. The second is based on the carry feed-forward adder structure which results in the first reported square-root architecture that can be pipelined down to the bit-level. Furthermore, there is no specification of the type of adder used in the CAS cell. It can be a carry look-ahead or a carry propagate adder. The proposed architecture is general for any digit size and any wordlength.

Radix digit-serial pipelined divider/square-root architecture

The paper presents a new digit-serial architecture for division and square-root which can be pipelined to the bit level to achieve high throughput. The architecture is different from the existing divider/square-root architectures in that it is based on the radix-2n algorithm. As a result, any type of adder can be used in the proposed digit-serial controlled add/subtract basic cell. The authors present two basic digit-serial controlled add/subtract cells. The first is based on the conventional carry feedback digit-serial adder. The second is based on the carry feed-forward adder, which results in the first reported digit-serial divider/square-root architecture that can be pipelined down to the bit-level. An evaluation of the proposed architecture for different values of the digit size is also presented.

A case for digit serial VLSI signal processors

Digit serial architectures, which have digit serial data transmission combined with digit serial computation, are uniquely suited for the design of VLSI signal processors. The speed disadvantages of digit serial input are overcome if the input is overlapped with the computation--what we refer to as digit pipelining. Digit pipelining allows us to break up long strings of combinatorial logic and, thus, to increase the clock rate of the system while still preserving much of the circuit structure. In general, for a modest increase in hardware (which in VLSI translates to a modest increase in area) digit serial architectures offer the potential of higher throughput than equivalent word parallel architectures. Several designs for various digit serial adders are presented. Then two filter examples are discussed that use the digit serial adders to achieve digit pipelining.