Differential Opamp Research Articles

A High-Speed Fully Differential Telescopic Op-Amp for Active Filter Designs in V2X Applications

In this paper, an ultra-wideband fully differential two-stage telescopic 65-nm CMOS op-amp is presented, which uses low-voltage design techniques such as level shifter circuits and low-voltage cascode current mirrors. The designed op-amp consists of two stages. While the telescopic first stage provides high speed and low swing, the second stage provides high gain and large swing. Common-mode feedback circuits (CMFB), which contain five transistors OTA and sensing resistors, are used to set the first-stage output to a known value. The designed two-stage telescopic operational amplifier has 41.04[Formula: see text]dB lower frequency gain, 1.81[Formula: see text]GHz gain-bandwidth product (GBW) and 51.9∘ phase margin under 5[Formula: see text]pF load capacitance. The design consumes a total current of 11.9[Formula: see text]mA from a 1.2-V supply voltage. Presented fully differential two-stage telescopic op-amp by using low-voltage design techniques is suitable for active filter in vehicle-to-everything (V2X) applications with 120[Formula: see text][Formula: see text]m[Formula: see text]m layout area.

A Fast and Fully Parallel Analog CMOS Solver for Nonlinear PDEs

A general-purpose analog computing method is proposed to compute the continuous-time solutions of nonlinear partial differential equations (PDEs). The discrete-time difference operator in the standard finite difference time domain (FDTD) method is replaced by continuous-time delay operators that can be realized using analog all-pass filters. The resulting spatially discrete time-continuous (SDTC) update equations are realized using analog circuits which compute continuous-time solutions of the PDE with prescribed initial and boundary conditions. The proposed concept is demonstrated in simulation via an integrated circuit (IC) design of a nonlinear acoustic wave equation solver in 180 nm CMOS technology. Analog arithmetic operations (multiply, scale, and add) are realized in parallel using fully differential op-amps and analog multipliers. The proposed IC computes the PDE solution in parallel at 33 discrete spatial points and has a simulated bandwidth and power consumption of approximately 2 MHz and 3 W, respectively. The performance of the IC is simulated using foundry-supplied device models and quantified using i) the mean squared difference between the circuit simulation results and FDTD simulations, and ii) the noise to signal energy ratio. Acceptable accuracy is obtained, with error metric values varying between -7 and -30 dB for various configurations of the problem. Comparison of the custom analog IC simulations with MATLAB- and C-based FDTD code running on a modern workstation shows an expected average speedup of 205× and 140×, respectively.

Design and simulation of high-swing fully differential telescopic Op-Amp

This article describes the process of design and simulation of a high-swing fully differential telescopic operational amplifier (Op-Amp). Due to the common gate-common source (CG and CS) cascode structure, the gain is very high. To maximize this gain, the load must also be selected such as two current sources. This circuit has the higher voltage in output than current Op-Amps in accordance with desirable characteristics. The loss of power of this operating amplifier are very low and in milliwatts. With use of a power supply of 1.8 V, it achieves a high-swing 1.2 V, a differential gain of 76.333 dB, ωuGB of 412 MHz, and >50 dB CMRR. This new design through the simulations and analytically shows that the high-swing fully differential telescopic Op-Amp retains its high CMRR even at high frequencies.

Design and simulation of high-swing fully differential telescopic Op-Amp

This article describes the process of design and simulation of a high-swing fully differential telescopic Operational Amplifier (Op-Amp). Due to the Common Gate-Common Source (CG and CS) cascode structure, the gain is very high. To maximize this gain, the load must also be selected such as two current sources. This circuit has the higher voltage in output than current Op-Amps in accordance with desirable characteristics. The loss of power of this operating amplifier are very low and in milliwatts. With use of a power supply of 1.8 V, it achieves a high-swing 1.2 V, a differential gain of 76.333 dB, ω_uGB of 412 MHz, and 50 dB CMRR. This new design through the simulations and analytically shows that the high-swing fully differential telescopic Op-Amp retains its high CMRR even at high frequencies.

Ultra-Wide Bandwidth Fully Differential CMOS Opamp with a Novel Bandwidth Extension Technique for SoC Active Filter Applications

An ultra-wide bandwidth fully differential two-stage 65[Formula: see text]nm CMOS operational amplifier (Opamp) is presented, which uses a novel bandwidth extension technique called “pole duplication”. This technique is based on relocating the dominant pole with the same location with a non-dominant pole and adjusting 3-dB frequency and stability with a compensation network. Simulation results show that the proposed Opamp has 103[Formula: see text]MHz 3-dB bandwidth with a 2[Formula: see text]pF load capacitor. It consumes 9[Formula: see text]mA current from 1.2-V supply. Transition frequency of 2.4[Formula: see text]GHz and a gain of 29[Formula: see text]dB is accomplished. A 2[Formula: see text]pF load capacitance can be driven at a phase margin of [Formula: see text]. The suggested pole duplication technique is used to achieve higher 3-dB cut-off frequencies by adjusting the load capacitor. Fully differential two-stage Opamp is presented, which uses a novel bandwidth extension technique, is suitable for SoC active filter applications with 40[Formula: see text][Formula: see text]m layout area and ultra-wide 3-dB bandwidth.

Improvement of Gain Accuracy and CMRR of Low Power Instrumentation Amplifier Using High Gain Operational Amplifiers

Background: Sensing of biomedical signals is crucial for monitoring of various health conditions. These signals have a very low amplitude (in μV) and a small frequency range (<500 Hz). In the presence of various common-mode interferences, biomedical signals are difficult to detect. Instrumentation amplifiers (INAs) are usually preferred to detect these signals due to their high commonmode rejection ratio (CMRR). Gain accuracy and CMRR are two important parameters associated with any INA. This article, therefore, focuses on the improvement of the gain accuracy and CMRR of a low power INA topology. Objective: The objective of this article is to achieve high gain accuracy and CMRR of low power INA by having high gain operational amplifiers (Op-Amps), which are the building blocks of the INAs. Methods: For the implementation of the Op-Amps and the INAs, the Cadence Virtuoso tool was used. All the designs and implementation were realized in 0.18 μm CMOS technology. Results: Three different Op-Amp topologies namely single-stage differential Op-Amp, folded cascode Op-Amp, and multi-stage Op-Amp were implemented. Using these Op-Amp topologies separately, three Op-Amp-based INAs were realized and compared. The INA designed using the high gain multistage Op-Amp topology of low-frequency gain of 123.89 dB achieves a CMRR of 164.1 dB, with the INA’s gain accuracy as good as 99%, which is the best when compared to the other two INAs realized using the other two Op-Amp topologies implemented. Conclusion: Using very high gain Op-Amps as the building blocks of the INA improves the gain accuracy of the INA and enhances the CMRR of the INA. The three Op-Amp-based INA designed with the multi-stage Op-Amps shows state-of-the-art characteristics as its gain accuracy is 99% and CMRR is as high as 164.1 dB. The power consumed by this INA is 29.25 μW by operating on a power supply of ±0.9V. This makes this INA highly suitable for low power measurement applications.

An ISM Band High-Linear Current-Reuse Up-Conversion Mixer With Built-in-Self-Calibration for LOFT and I/Q Imbalance

This brief presents a high-linear current-reuse upconversion mixer with built-in-self-calibration for LO feed through (LOFT) and I/Q imbalance for the 2.4GHz ISM band transmitter. Exploiting the negative feedback loop and the saturated switches biased by the current bleeding, third-order intermodulation (IM3) products are eliminated. Based on the fully differential push-pull OP-AMP and current mirror, the current-reuse input transconductance with a boosted gain is achieved. LOFT and I/Q imbalance calibrations are carried out utilizing two fully-integrated auto-calibration loops with the auto-zero comparator and the low noise envelope detector, respectively. Fabricated in 40 nm LP CMOS technology, the mixer shows 15.02 dBm OIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> and -1.80 dBm OP1dB while consuming 12.75 mW from 1.1 V power supply for 4.17 dB gain. Along with the third-order filter, the up-conversion mixer achieves >40 dBc LO suppression ration (LSR) and 50.6 dBc image rejection ration (IMRR) within ±2 dB deviation among 10 MHz bandwidth, thanks to the two calibration loops.

Third-Order Low-Pass Filters for Limiting the Signal Spectrum at the Differential Input of the Analog/Digital Converters

Two new architectures of the third-order low-pass filters (LPF) based on differential (Op-Amp) and differential difference amplifiers (DDA) with a paraphase output are compared. This architectures designed for practical use as anti-aliasing filters in analog-to-digital converters of sensor signals of various physical quantities. The basic equations of the developed LPF modifications that make possible to perform their parametric synthesis are given. The computer simulation results are presented, which show that the LPFs under consideration provide the guaranteed frequency response (FR) attenuation outside the bandwidth being implemented on Op-Amps by Analog Device (AD8132) and Texas Instruments (THS4131).

Research on Two stage and Folded Cascode Bulk Driven OTA in 0.18um CMOS Process

This paper presence a comparative analysis of two stage and folded cascode bulk driven operational trans conductance amplifier (OTA) topologies for biomedical applications are presented. A two stage bulk driven OTA and Folded cascoded OTA operated with a 1Vpower supply. Bulkdriven PMOS-transistors as an input differential opamp provides high input common-mode range (CMR). To achieve low power consumption all transistors must be operated in sub threshold region. The test results are carried out in standard gpdk180nm CMOS technologies

Research on Two Stage and Folded Cascode Bulk Driven OTA in 0.18um CMOS Process

This paper presence a comparative analysis of two stage and folded cascode bulk driven operational trans conductance amplifier (OTA) topologies for biomedical applications are presented. A two stage bulk driven OTA and Folded cascoded OTA operated with a 1Vpower supply. Bulkdriven PMOS-transistors as an input differential opamp provides high input common-mode range (CMR). To achieve low power consumption all transistors must be operated in sub threshold region. The test results are carried out in standard gpdk180nm CMOS technologies.

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.

An efficient method of Pareto-optimal front generation for analog circuits

In this paper, an efficient deterministic methodology for generating Pareto-optimal front (PoF) of analog circuits is proposed. The proposed methodology utilizes modified epsilon constraint method along with geometric programming based circuit sizer to determine the Pareto-optimal points (PoPs) of the analog circuits. The generated PoPs are then modeled to generate the PoFs. The efficiency of the proposed methodology and the accuracy of the generated PoF has been verified with respect to that of the commonly used stochastic approach. It is found that to generate PoF having similar spread, the proposed methodology takes only 20 min whereas the stochastic approach takes 60 h. It also has been observed that the accuracy of the generated PoF using the proposed methodology improved by more than 10% with respect to that of the stochastic approach. The proposed methodology has been implemented to generate the PoF of a two-stage Op-Amp, fully differential folded cascode Op-Amp, fully differential single-stage and two-stage Op-Amps. The generated PoFs have been utilized for (1) feasibility checking for a user given specification of an Op-Amp, (2) performance prediction and (3) topology selection of the analog circuit. As per authors’ knowledge, this is the first paper which deals with all the aspects, i.e., generation, modeling and application of the PoF of the analog circuits.

Readout Circuits for Noise Compensation in ISFET Sensory System

This paper presents two different noise reduction techniques for ion sensitive field effect transistor (ISFET) readout configuration and their comparison. The proposed circuit configurations are immune to the noise generated from the ISFET sensory system and particularly to the low frequency pH dependent 1/f electrochemical noise. The methods used under this study are compensation of noise by differential OPAMP based and Wheatstone bridge circuit, where two identical commercial ISFET sensors were used. The statistical and frequency analysis of the data generated by this two methods were compared for different pH value ranging from pH 2 to 10 at room temperature, and it is found that the readout circuits are able to compensate the noise to a great extent.

A Model-Agnostic Technique for Simulating Per-Element Distortion Contributions

The nonlinearity of an element can be altered while retaining the original operating point and first-order terms by appropriately combining multiple instances of the nonlinear element. Each instance of the combination is biased at the same operating point as the original element, but is driven by a scaled version of incremental signal present across the latter. Maintaining the sum of scaling factors over all instances to be unity preserves first-order behavior. Substituting an element in a weakly nonlinear circuit with its composite counterpart changes the contribution of that element to the output distortion. Per-element distortion contributions in a weakly nonlinear circuit can then be determined by substituting the relevant element by the composite element, altering its nonlinear terms by known factors, and simulating the output distortion in each case. This technique can be used in a standard circuit simulator which implements the appropriate nonlinear device models, but, crucially, requires no knowledge of the device model details on the part of the circuit designer. The principle is demonstrated by applying it to a common source amplifier with a nonlinear load, a second order RC filter with nonlinear resistors, and a two stage fully differential opamp.

DESIGN AND ANALYSIS OF LOW POWER PSEUDO DIFFERENTIAL CLASS-AB TELESCOPIC OPERATIONAL AMPLIFIER

In this paper, the design of a pseudo differential class-AB cascoded telescopic op-amp for a 10-bit pipelined ADC is presented. A pseudo differential class-AB telescopic op-amp is used for the ADC architecture because of its large signal swing and high power efficiency. To further enhance the dc gain of the pseudo differential class-AB cascoded telescopic op-amp, two additional load capacitors are used. This proposed amplifier is designed in 180nm CMOS technology, and the simulation results show rail-to-rail input and output swings. With the modified pseudo differential class-AB cascoded telescopic op-amp the DC gain obtained is 43.41dB. The Common mode Rejection Ratio (CMRR) is 43.4dB, 91.19747° phase margin, 165.4544V/µs slew rate with 8-pF load capacitor and the power consumption is 0.4mW.

A 97 dB 400 MHz rail to rail fully differential opamp based on split length FGMOS-MOS cell

Recently introduced MOS-FGMOS split length cell has been used to increase the DC gain of a fully differential op amp. Resultant proposed opamp structure exhibits gain of 97 dB and unity gain bandwidth of 400 MHz with power consumption of 1.2 mW. An opamp design has been verified with Cadence Spectre using a 130 nm technology at 1.2 V and has a slew rate of $$53\,\hbox {V}/\mu \hbox {s}$$ 53 V / μ s with a phase margin of $$78^{\circ }$$ 78 ? .

Fully Differential Op-Amp Is Designed Using The Proposed Compensation Scheme

This paper concerns the design and implementation of CMOS operational amplifier with current mirror load in 0.18um process to satisfy some specifications such as,: VDD = 1.8V, SR >= 10V/us (CL = 2pF), phase margin 60 0 , f-3dB>= 100kHz (CL = 2pF), a small signal gain A >=1000 V/V, ICMR is (0.7V, 1.1V) and Pdiss<=1mW.And shows DC response, AC response, and transient response. CMOS gates are not particularly effective in detecting and reacting to small signal changes, because of the relatively small transconductance of the MOS device. In order to work properly and to achieve high performance, reduced-swing circuits normally require amplifier circuits, whose task it is to restore the signal to its full swing in a minimum amount of time and with a minimum amount of extra energy consumption.

A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

A 0.1---4 GHz software-defined radio (SDR) receiver with reconfigurable 10---100 MHz signal bandwidth is presented. The complete system design methodology, taking blocker effects into account, is provided. Fully differential Op-Amp with Miller feedback and feed-forward compensations is proposed to support wideband analog circuits with low power consumption. The stability and isolation of inverter-based trans-conductance amplifier are analyzed in details. The design approach of high linearity Tow-Thomas trans-impedance amplifier is presented to reject out-of-band blockers. To compensate for PVT variations, IIP2, frequency tuning, DC offset and IQ calibration are also integrated on-chip. The SDR receiver has been implemented in 65 nm CMOS, with 1.2/2.5 V power supply and a core chip area of 2.4 mm2. The receiver achieves S11 input matching below ?10 dB and a NF of 3---8 dB across the 0.1---4 GHz range, and a maximum gain of 82---92 dB with a 70 dB dynamic range. Dissipated power spans from 30 to 90 mW across this entire frequency range. For LTE application with 20 MHz signal bandwidth and a LO frequency of 2.3 GHz, the receiver consumes 21 mA current.

A Novel High-Pass Filters Implementation by Fully Differential Op Amp Integrators

The design of low-pass and bandpass filters is often based on the leapfrog method which, in these cases, yields integrator-based structures. Using the leapfrog signal flow graph (SFG) for the simulation of high-pass filters leads to a differentiator-based structure which could be implemented by Gm-C or CCII conveniently. However, when we use Op amp RC integrators for good linearity, we have to use integrators, and not differentiators, for reasons related to the excessive noise behavior of the latter. This paper presents a new leapfrog SFG implementation by fully differential Op amp integrators, which combines good high-frequency properties with good noise properties. The direct SFG simulation method and single-ended output Op amp can also based on integrators, but all of them will lead to a relatively high circuit complexity and a high noise level. A design example is included, with comparisons of gain responses and noise densities.

Wideband pulse amplifiers for the NECTAr chip

The NECTAr collaboration's FE option for the camera of the CTA is a 16bits and 1–3GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20V/V and a BW of 400MHz. As it is impossible to design a fully differential OpAmp with an 8GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.