Differential Current-mode Logic Research Articles

A 10-Gb/s 20-ps Delay-Range Digitally Controlled Differential Delay Element in 45-nm SOI CMOS

This brief presents a 4-bit digitally controlled differential delay element (DCDE) with high-speed and high-resolution capability, two challenging requirements in the design of delay elements. Two input bits, inside the differential current-mode logic (CML) DCDE, regulate its bias current and the resistive load, while the other two bits configure the output capacitive load enabling the presented DCDE to achieve a phase shift of 20 ps and an average resolution of 1.25 ps. Designed in 45-nm silicon-on-insulator (SOI) CMOS, the DCDE dissipates 4 mW of power under maximum biasing condition and can operate up to 10 Gb/s while adding only 0.6 ps of root-mean-square jitter to the delayed input. To the best of authors knowledge, the designed DCDE is the first 4-bit low-jitter 10-Gb/s variable-load CML DCDE offering a time resolution of 1.25 ps, making it a suitable candidate for high-speed and high-resolution applications.

An InGaAs/InP 40 GHz CML static frequency divider

Static frequency dividers are widely used as a circuit performance benchmark or figure-of-merit indicator to gauge a particular device technology's ability to implement high speed digital and integrated high performance mixed-signal circuits. We report a 2 : 1 static frequency divider in InGaAs/InP heterojunction bipolar transistor technology. This is the first InP based digital integrated circuit ever reported on the mainland of China. The divider is implemented in differential current mode logic (CML) with 30 transistors. The circuit operated at a peak clock frequency of 40 GHz and dissipated 650 mW from a single −5 V supply.

CMOS Latch Using Quad for High-Speed Comparators

The well-known CMOS quad consisting of two asymmetric differential pairs is a transconductance element. It provides an additional output current proportional to the square of its differential input voltage. Here, we use both the linear and square-law outputs of a quad to build a high-speed latch that has differential low-voltage output swing. This latch retains the useful property of constant power-supply current like all current-biased differential current-mode logic circuits. Simulation results for 0.18-mum CMOS process are presented. The design is application specific and is intended for use in high-speed comparators needed for analog-to-digital converters

Counting and Integrating Readout for Direct Conversion X-ray Imaging: Concept, Realization and First Prototype Measurements

A novel signal processing concept for X-ray imaging with directly converting pixelated semiconductor sensors is presented. The novelty of this approach compared to existing concepts is the combination of charge integration and photon counting in every single pixel. Simultaneous operation of both signal processing chains extends the dynamic range beyond the limits of the individual schemes and allows determination of the mean photon energy. Medical applications such as X-ray computed tomography can benefit from this additional spectral information through improved contrast and the ability to determine the hardening of the tube spectrum due to attenuation by the scanned object. A prototype chip in 0.35-micrometer technology has been successfully tested. The pixel electronics are designed using a low-swing differential current mode logic. Key element is a configurable feedback circuit for the charge sensitive amplifier which provides continuous reset, leakage current compensation and replicates the input signal for the integrator. This paper will discuss measurement results of the prototype structures and give details on the circuit design

Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic

A NULL-convention circuit based on dual-rail current-mode differential logic is proposed for a high-performance asynchronous VLSI. Since input/output signals are mapped to dual-rail current signals, the NULL-convention circuit can be directly implemented based on the dual-rail differential logic, which results in the reduction of the device counts. As a typical example, a NULL-convention logic based full adder using the proposed circuit is implemented by a 0.18 μm CMOS technology. Its delay, power dissipation and area are reduced to 61 percent, 60 percent and 62 percent, respectively, in comparison with those of a corresponding CMOS implementation.

A 2-GHz clocked AlGaAs/GaAs HBT byte-slice datapath chip

A byte-slice datapath for exploring multi-chip RISC processor development in AlGaAs-GaAs heterojunction bipolar transistor (HBT) technology has been designed, fabricated and tested. The circuits are implemented using differential current-mode logic (CML) and emitter-coupled logic (ECL) with signal swings of 250 mV. Each datapath chip contains a single slice, including an 8-bit by 32-word single-port register file with a 230-ps read access time, and an 8-bit carry-select adder with a 140-ps select path and a 380-ps ripple-carry path. Each unpackaged die was tested using an at-speed boundary scan test scheme. The register file and adder carry chain are also implemented in a special test chip for accurate performance characterization of these critical circuits.

Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy

Integrated-circuit interconnect characterization is growing in importance as devices become faster and smaller. Along with this trend, interconnect geometry is becoming more complex, consisting of an increasing number of wiring levels. Accurate numerical extraction of three-dimensional (3-D) interconnect capacitance is essential for achieving design targets in the multigigahertz digital regime. Interconnect-capacitance extraction is complicated by the presence of inhomogeneous layers with differing dielectric constant. Dielectric anisotropy as well is common in many low-/spl kappa/ polymeric dielectrics used in high-performance ICs. A CAD procedure using the novel floating random-walk extractor QuickCAP is presented. Our procedure is efficient enough to extract a substantial amount of a chip's 3-D wiring. We include as well dielectric anisotropy and inhomogeneity. The procedure is not based on effective conductor geometry or on a finite-sized conductor library but rather on the entire 3-D layout, accounting for actual local variations in conductor separations and shapes. We then apply our procedure to an experimental circuit vehicle implemented in AlGaAs-GaAs heterojunction bipolar transistor current-mode logic. This vehicle is used to validate the accuracy of our CAD procedure in predicting circuit speed. Measured and predicted test-capacitor values and ring-oscillator propagation times agreed generally to within 2-4%. To verify results on a larger digital circuit, we analyzed all interconnects in an adder carry-chain oscillator using our procedure. Predicted propagation delays were generally within 3% of measurement.

Design and evaluation of a multiple-valued arithmetic integrated circuit based on differential logic

A design of a new multiple-valued current-mode circuit for high-speed arithmetic systems is presented. The use of a differential logic circuit with dual-rail complementary inputs makes a signal-voltage swing small with a constant driving current, so that the delay of the circuit can be reduced. As an application to arithmetic systems, it is demonstrated that the operating speed of the radix-2 signed-digit (SD) adder based on multiple-valued current-mode differential logic is 1.3 times faster than that of the corresponding binary CMOS implementation at a 3.5 V supply voltage.

Modulation-doped FET DCML comparator

A differential current mode logic (DCML) comparator has been inplemented with modulation-doped FET technology. The dynamic input/output hysteresis is low enough to realise a flash quantiser with up to 5-bit accuracy.

High Precision High Speed Analog/Digital LSI Techniques

Techniques have been developed to produce high accuracy (0.1%) analog digital monolithic circuits at 50 to 100 MHz rates. The techniques involve a high speed ion implanted bipolar process with integrated thin film cermet resistors, the use of differential current mode logic, and careful circuit design. Several high speed A/D converters have been developed using these techniques, including a 10 bit, 5 MS/s A/D that is timed with a 60 MHz clock.