Differential CMOS Low Noise Amplifier Research Articles

Design of 130nm RFCMOS differential low noise amplifier

<span>In this paper, an inductively degenerated CMOS differential low noise amplifier circuit topology is presented. This low noise amplifier is intended to be used for wireless LAN application. The differential low noise amplifier proposed provide high gain, low noise and large superior out of band IIP3. The LNA is designed in 130 nm CMOS technology. Simulated results of gain and NF at 2.4GHz are 20.46 dB and 2.59 dB, respectively. While the simulated S<sub>11</sub> and S<sub>22</sub> are −11.18 dB and −9.49 dB, respectively. The IIP3 is −9.05 dBm. The LNA consumes 3.4 mW power from 1.2V supply. </span>

Differential CMOS Low Noise Amplifier Design for Wireless Receivers

This article presents the differential CMOS-LNA design for wireless receiver at the frequency of 3.4GHz. This differential provides less noise figure (NF), high gain and good reverse isolation as well as good stability. The designed LNA is simulated with a 180 nanometers CMOS process in cadence virtuoso tool and simulate the results by using SpectreRF simulator. This LNA exhibits a NF of 0.7dB, a high voltage gain of 28dB, and good reverse isolation (S12) of -70dB. It produces an input and output reflection coefficient (S11) of -6.5dB and (S22) of -14dB, and it maintains good stability of Rollet factor Kf > 1, and also alternate stability factor B1f < 1, respectively.

Linearity improvement of differential CMOS low noise amplifier

<p>This paper presents the linearity improvement of differential CMOS low noise amplifier integrated circuit using 0.13um CMOS technology. In this study, inductively degenerated common source topology is adopted for wireless LAN application. The linearity of the single-ended LNA was improved by using differential structures with optimum biasing technique. This technique achieved better LNA and linearity performance compare with single-ended structure. Simulation was made by using the cadence spectre RF tool. Consuming 5.8mA current at 1.2V supply voltage, the designed LNA exhibits S<sub>21</sub> gain of 18.56 dB, noise figure (NF) of 1.85 dB, S<sub>11</sub> of −27.63 dB, S<sub>22</sub> of -34.33 dB, S<sub>12</sub> of −37.09 dB and IIP3 of -7.79 dBm.</p>

A 9 - 10.6 GHz Microstrip Antenna—UWB Low Noise Amplifier with Differential Noise Canceling Technique for IoT Applications

An ultra-wide band (UWB) receiver front-end that operates at the UWB frequency range, starting from 9 GHz - 10.6 GHz is proposed in this paper. The proposed system consists of an off-chip microstrip antenna and CMOS differential low noise amplifier with a differential noise canceling (DNC) technique. The proposed antenna is trapezoidal dipole shaped with balun and printed on a low-cost FR4 substrate with dimensions 10 × 10 × 0.8 mm3. The balun circuit integrated with the ground antenna to improve the antenna impedance matching. Noise canceling is obtained by using a differential block with each stage having 2 amplifiers that generate differential signals, subtracted to improve total noise performance. The proposed DNC block improves NF by 50% while increasing total power consumption with only 0.1 Mw. The differential CMOS cascode LNA with DNC block is implemented using UMC 0.13 μm CMOS process, exhibits a flat gain of 19 dB, maximum noise figure of 2.75 dB, 1 dB compression point −16 dBm and 3rd order intercept point (IIP3) −10 dBm. The proposed system has total DC power consumption of 2.8 mW at 1.2 V power supply.

A full-band UWB common-gate band-pass noise matched g m -boosted series peaked CMOS differential LNA

This paper presents a low-power noise-matched fully-differential common-gate (CG) low noise amplifier (LNA) for ultrawideband receiver operating in the full 3.1---10.6 GHz band. Performance was optimized by employing the transconductance `g m ' boosted CG LNA topology with series peaking along with an input noise matching network. A common source g m -boosting amplifier, in conjunction with an LC T-network, was used to share the bias current with the CG stage. The LNA was demonstrated using a 130 nm IBM CMOS process technology and it consumed 7 mW from a 1 V supply. It exhibited an input return loss (S11) and an output return loss (S22) of ?10.5 and ?14 dB respectively. In addition, it also achieved a forward power gain (S21) of 14.5 dB and a noise figure between 4.5 and 5.0 dB.

Series peaked noise matched gm-boosted 3.1–10.6 GHz CG CMOS differential LNA for UWB WiMedia

A low-power noise-matched fully-differential common-gate (CG) low-noise amplifier (LNA) is presented for ultra-wideband (UWB) operating in the 3.1–10.6 GHz band. Performance was optimised by employing the transconductance ‘gm’-boosted CG LNA topology with series peaking along with an input noise matching network. A common source gm-boosting amplifier, in conjunction with an LC T-network, was used to share the bias current with the CG stage. The LNA was demonstrated using 130 nm CMOS process and consumed 7 mW from a 1 V supply. It exhibited an input return loss (S11) and an output return loss (S22) of −10.5 dB and −14 dB, respectively. Also, it achieved a forward power gain (S21) of 14.5 dB and a noise figure between 4.5 and 5.0 dB.

A Packaged and ESD-Protected Inductorless 0.1–8 GHz Wideband CMOS LNA

In this letter, an inductorless 0.1-8 GHz wideband CMOS differential low noise amplifier (LNA) based on a modified resistive feedback topology is proposed. Without using any passive inductors, the modified resistive feedback technique implemented with a parallel R-C feedback, an active inductor load, and neutralization capacitors achieves high gain, low noise, and good return loss over a wide bandwidth. To ensure the robustness in the system integration, electro-static discharge diodes are added to the radio frequency pads. The LNA was fabricated using a digital 90 nm CMOS technology. It achieves a 3 dB bandwidth of 8 GHz with a 16 dB voltage gain, noise figures from 3.4 dB to 5.8 dB across the whole band, and an input third-order intermodulation product (IIP3) of -9 dBm. The active area of the chip is 0.034 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The chip was packaged and tested on an FR4 PCB using the chip-on-board approach.

A high-gain differential CMOS LNA for 3.1-10.6GHz ultra-wideband receivers

This paper presents a high-gain differential CMOS low noise amplifier (LNA) for 3.1-10.6GHz ultra-wideband receivers. A novel structure that combines capacitive cross-coupling common-gate topology with common-source topology is proposed, which increases the power gain greatly and imposes little impact on other performances of the LNA.The LNA is designed in the TSMC 0.18µm CMOS technology. Post-layout simulation results show that the LNA achieves a power gain of 14.9 ∼ 16dB and a noise figure of 3.5 ∼ 4.9dB with a current consumption of 6.3mA from a 1.8V power supply. The layout area is 0.7 × 0.9mm2.

A 2-dB noise figure 900-MHz differential CMOS LNA

This paper proposes a new circuit topology for RF CMOS low noise amplifier (LNA). Since pMOS devices are approaching the performances of nMOS devices in scaled technologies, the idea is to realize the input stage shunting an inductively degenerated nMOS stage with a pMOS one. In this way, due to the inherent current reuse, the performances can be improved using the same power consumption. Since the devices of an inductively degenerated input stage are working in moderate inversion (at least at moderate power dissipation), prior to the stage optimization an appropriate moderate inversion model is introduced. A fully differential 900-MHz 0.35-/spl mu/m CMOS LNA (plus output buffer) prototype achieves the following performances: 2-dB noise figure (NF), 17.5-dB power gain, -6-dBm IIP3 with 8-mA current consumption from a 2.7-V voltage supply. To the author's knowledge, this is the lowest reported NF for a fully differential CMOS LNA operating at this power consumption level. As an additional feature, this LNA has a programmable gain.