Differential Cascade Voltage Switch Logic Research Articles

Implementation and Comparative Analysis of Low Power Multiplexers Using Dynamic Logic Styles

This paper presents the implementation and comparative analysis of low power multiplexers using dynamic logic styles. A multiplexer is a digital circuit with 2N input lines with N selection lines and gives a single output. Dynamic logic styles were used in conventional CMOS for optimizing power, area, and delay, etc. Different types of dynamic logic styles such as complementary CMOS, pseudo NMOS, domino differential cascade voltage switch logic, low power feed through logic, and clocked CMOS logic were used for the implementation of a multiplexer. In this present work, the implementation of 2:1 multiplexer using different dynamic logic styles with various technologies (120nm, 90nm, 70nm) and the performance parameters such as power consumption and delay were compared and analyzed. The clocked CMOS was found efficient in low power consumption and fast switching speed. Among the different logic styles, Domino, clocked and low power feed through logic produces efficient in delay and power consumption. The implementation and simulation of low power multiplexers were carried out by using DSCH 2.6F microwind tool.

Implementation of Low Power Null Conventional Logic Function for Configuration Logic Block

Todays, transistor level design plays major impact in the power consumption of the VLSI based design. The various logic design models are used to reduce the power consumption that includes synchronous and asynchronous design model. The operation of synchronous circuit is limited by the in phase factor of the clock pulse signal which is used to control the synchronous circuit. In contrast, asynchronous circuits are used widely because it causes low noise, require less power. It affects the less electromagnetic interference that allows reuse of the components. These asynchronous circuits are being implemented by Null Conventional Logic (NCL) which is a delay insensitive logic model. The Configuration Logic Block is the power consuming model in Field Programmable Gate Array (FPGA). This block contains the lookup table (LUT) and 27 fundamental NCL logic gates. To reduce the power consumption of this module, we use the Differential Cascade Voltage Switch Logic (DVSL). The power reduction is achieved in LUT by means of DVSL and minimizes the number transistors. This NCL, DVSL, FPGA logic element is simulated using 90 nm TSMC CMOS processing technology.

Calibration method to reduce the error in logarithmic conversion with its circuit implementation

Here, based on Mitchell's logarithmic conversion, the authors propose a fast calibration method using a fixed binary code with case judgement, which suppresses the conversion error. The authors developed a highly paralleled circuit serving the proposed calibration method. Differential cascade voltage switch logic (DCVSL) is used to work in both high-speed logic and adiabatic logic and trade-off between power dissipation and operation speed. In addition, a low-cost adiabatic clock generator without any passive component is presented to support a four-phase sine clock for the adiabatic logic operation. An 8-bit logarithmic converter is designed in TSMC 180 nm CMOS. Post-simulation results show that the proposed calibration can reduce the conversion error to 1.55% based on Mitchell's algorithm, the power dissipation varies between 1.12 and 3.709 mW, and the delay is 1.82 ns under operational DCVLS.

Miller effect suppression of tunnel field‐effect transistors (TFETs) using capacitor neutralisation

A novel method of suppressing the Miller effects of tunnel field-effect transistors (TFETs) is proposed by using capacitor neutralisation. Since TFETs suffer from more severe Miller effects than metal-oxide-semiconductor FETs, conventional ways such as short-gate structures are not sufficient to fully suppress the Miller effects of TFETs. For further reduction of Miller effects, capacitor neutralisation is applied to TFET circuit design for the first time. An exemplary circuit has been shown to confirm the effectiveness of capacitor neutralisation such as differential cascade voltage switch logic. The suppression of Miller effects has been discussed in terms of undershoot, switching delay, power consumption and circuit area.

Simulation study of N-hit SET variation in differential cascade voltage switch logical circuits

The advancement in the process leads to more concern about the Single Event (SE) sensitivity of the Differential Cascade Voltage Switch Logic (DCVSL) circuits. The simulation results indicate that the Single Event Transient (SET) generated at the DCVSL gate is much larger than that at the ordinary CMOS gate, and their SET variation is different. Based on charge collection, in this paper, the effective collection time theory is proposed to set forth the SET pulse generated at the DCVSL gate. Through 3D TCAD mixed-mode simulation in 65 nm twin-well bulk CMOS process, the effects on SET variation of device parameters such as well contact size and environment parameters such as voltage are investigated.

Efficient Hardware Trojan Detection with Differential Cascade Voltage Switch Logic

Offshore fabrication, assembling and packaging challenge chip security, as original chip designs may be tampered by malicious insertions, known as hardware Trojans (HTs). HT detection is imperative to guarantee the chip performance and safety. Existing HT detection methods have limited capability to detect small-scale HTs and are further challenged by the increased process variation. To increase HT detection sensitivity and reduce chip authorization time, we propose to exploit the inherent feature of differential cascade voltage switch logic (DCVSL) to detect HTs at runtime. In normal operation, a system implemented with DCVSL always produces complementary logic values in internal nets and final outputs. Noncomplementary values on inputs and internal nets in DCVSL systems potentially result in abnormal power behavior and even system failures. By examining special power characteristics of DCVSL systems upon HT insertion, we can detect HTs, even if the HT size is small. Simulation results show that the proposed method achieves up to 100% HT detection rate. The evaluation on ISCAS benchmark circuits shows that the proposed method obtains a HT detection rate in the range of 66% to 98%.

Implementation of Power Efficient Flash Analogue-to-Digital Converter

An efficient low power high speed 5-bit 5-GS/s flash analogue-to-digital converter (ADC) is proposed in this paper. The designing of a thermometer code to binary code is one of the exacting issues of low power flash ADC. The embodiment consists of two main blocks, a comparator and a digital encoder. To reduce the metastability and the effect of bubble errors, the thermometer code is converted into the gray code and there after translated to binary code through encoder. The proposed encoder is thus implemented by using differential cascade voltage switch logic (DCVSL) to maintain high speed and low power dissipation. The proposed 5-bit flash ADC is designed using Cadence 180 nm CMOS technology with a supply rail voltage typically ±0.85 V. The simulation results include a total power dissipation of 46.69 mW, integral nonlinearity (INL) value of −0.30 LSB and differential nonlinearity (DNL) value of −0.24 LSB, of the flash ADC.

Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors

This brief presents a novel power-gating technique for differential cascade voltage switch logic (DCVSL) based on double-gate (DG) controllable-polarity field-effect transistors (FETs). DG controllable-polarity FETs, commonly referred to as ambipolar transistors, are devices whose polarity is online reconfigurable by changing the second gate bias. In this brief, we exploit the online control of ambipolar device polarity to achieve intrinsically power-gated DCVSL circuits bypassing the use of series sleep transistors. We perform circuit-level simulations and comparisons at 22-nm technology node, considering silicon nanowire -based DG controllable-polarity FETs. Experimental results show that ambipolar DCVSL circuits power gated by the proposed technique have on average 6× smaller standby power with only 1.1× timing penalty with respect to their non-power-gated versions. As compared with unipolar FinFET-based realizations, our proposal is capable to reduce up to 1.9× the standby power consumption of a low-standby-power process and, at the same time, increase up to 10% the performance of a high-performance process.