Different Types Of Transistors Research Articles

Multi-objective optimization and inverse design of complementary field-effect transistor using combined approach of machine learning and non-dominated sorting genetic algorithms for next-generation semiconductor devices

Complementary field-effect transistors (CFETs), which are structures in which different types of transistors are vertically stacked with a shared control gate, are being focused on for continuing to satisfy Moore's law by overcoming the limitations in pitch scaling. The structures of semiconductor devices become more complex as technology node shrinks, and interrelated multivariate parameters increase. In addition, predicting problems and proposing solutions by identifying complex patterns within extensive data collected for emerging semiconductor designs pose significant computational challenges and are inherently difficult. As a breakthrough in design technology co-optimization for advanced devices, this study developed a novel optimization framework integrating technology computer-aided design simulations, machine learning, and non-dominated sorting genetic algorithms. The developed framework provides unbiased optimal solutions, even in a high-dimensional objective space, while considering the tradeoff relationships between multiple variables. In addition, it enables inverse design to identify the design parameters of devices that satisfy specific electrical performance criteria using only a forward model, while achieving an error rate of less than 2%. Using this framework, we analyzed the operational mechanism of CFETs by comparing the inverse designs of various devices. This novel approach is particularly important when the design space is complex and extensive and is well suited for developing devices that emerge with technological advancements in the semiconductor industry.

Monolithic Integration of GaN-Based Transistors and Micro-LED.

Micro-LED is considered an emerging display technology with significant potential for high resolution, brightness, and energy efficiency in display applications. However, its decreasing pixel size and complex manufacturing process create challenges for its integration with driving units. Recently, researchers have proposed various methods to achieve highly integrated micro-structures with driving unit. Researchers take advantage of the high performance of the transistors to achieve low power consumption, high current gain, and fast response frequency. This paper gives a review of recent studies on the new integration methods of micro-LEDs with different types of transistors, including the integration with BJT, HEMT, TFT, and MOSFET.

Low-energy complementary ferroelectric-nanocrack logic

Abstract Ferroelectric-based electronic devices have excellent low-energy characteristics due to the highly insulating property, in which the Joule heating can be neglected. The recent discovery of electrically switchable cracks in ferroelectric/alloy film heterostructure gave rise to a new way to construct transistor, where the opening and closing of crack switched the channel current off and on. Here, we observed the complementary switching of cracks for the first time, and demonstrated a complementary inverter without any additional process to set different types of transistors, which was implemented by forming the n- and p-type transistor in conventional complementary metal oxide semiconductor (CMOS) technology. The complementary states were generated spontaneously once the cracks were induced and varied with the change of applied input voltage polarity. The low ON resistance and near-zero OFF state leakage current result in the high current on/off ratio (~107) and allow for the low dynamic and static power dissipation. Further, the switching of cracks is coupled to the surrounding ferroelectric polarization states, offering the non-destructive readout operation. We believe that our work provides a very simple route to build complementary logic gates and paves a way for the energy-efficient electronic devices, while promoting the “crack nanoelectronics”.

(Invited) Challenges the UWBG Semiconductors AlGaN, Diamond, and Ga2O3 Must Master to Compete with SiC and GaN HPE Devices

Power diodes and transistors fabricated from the ultra-wide bandgap (UWBG) semiconductors, AlGaN, Ga2O3, and diamond using state-of-the-art materials are compared with those fabricated from GaN and SiC. Parameters used in the operation of the devices are discussed, methods for improving them are described, and the ability to, and importance of, improving them are assessed. Equations for the resistance of different elements of the device are also provided so one can assess their importance and make meaningful comparisons between the different types of transistors.

Radiation effect on silicon transistors in mixed neutrons–gamma environment

The effects of gamma and neutron irradiations on two different types of transistors, Junction Field Effect Transistor (JFET) and Bipolar Junction Transistor (BJT), were investigated. Irradiation was performed using a Syrian research reactor (RR) (Miniature Neutron Source Reactor (MNSR)) and a gamma source (Co-60 cell). For RR irradiation, MCNP code was used to calculate the absorbed dose received by the transistors.The experimental results showed an overall decrease in the gain factors of the transistors after irradiation, and the JFETs were more resistant to the effects of radiation than BJTs. The effect of RR irradiation was also greater than that of gamma source for the same dose, which could be because neutrons could cause more damage than gamma irradiation.

Fabrication of High Performance SWNT Film FETs in Unipolar p-Type, n-Type or Ambipolar Characteristics

A dense network of single wall carbon nanotubes (SWNTs) grown on a substrate is treated as a thin film to fabricate into a field effect transistor (FET) that can be made, for the first time in the literature, exhibiting either unipolar p-type, n-type or ambipolar characteristics by proper annealing for different gases. Different annealing conditions are made to find the clues or mechanisms leading to different types of transistors. The anneal with either O2 or N2 gas for the case when the SWNT network is covered with a HfO2 layer on top can make either donor or acceptor trap states to occur at the SWNT film/HfO2 interface. These trap states can accumulate either positive or negative charges during charge transfer process and cause suppression of either electron or hole conduction in the SWNT film and lead to either p-type or n-type FET. The SWNT FET fabricated is shown to have a much superior electronic properties than any of the FET made by single SWNT or amorphous silicon thin film transistors due to interconnection of the metal-semiconducting SWNT network. Fabrication of different types of SWNT Film FET allows fabrication of complementary SWNT FETs that can be used to assemble simple integrated circuits or logic devices in additional to the thin film transistors. Finally, the fabrication process used is simple (IC compatible) and cost effective which has the potential for later use in mass production.

$f_{\max}$ Improvement by Controlling Extrinsic Parasitics in Circuit-Level MOS Transistor

In this letter, f max improvement of a circuit-level radio-frequency (RF) transistor with systematic layout variations is presented in deep-submicrometer CMOS technology. We confirmed that the circuit-level MOS transistor has a tradeoff among the extrinsic capacitive and resistive parasitics (C gd, C gs, and Rg) on circular gate metal layers. Furthermore, it reduces the extrinsic C gd and Rg, which have great effect on the RF performance, simultaneously. For qualitative analysis of the capacitive coupling, which attributed to undesired extrinsic capacitance, capacitive coupling paths were separately defined as two cases, namely, direct capacitive coupling and indirect capacitive coupling. Some of the key small-signal parameters were also extracted and compared with different types of transistors, and they show a good match with the observed trends. The proposed layout exhibits the improvement of f max up to ~ 21% without fT variation compared to a reference device due to reduced extrinsic Rg and C gd parasitics by changing the number of gate contacts and gate-to-drain interconnection lines.

Characterization of pentacene based organic thin film transistor using conductive carbon electrode

AbstractAmorphous carbon films prepared by our experiments exhibited very low resistivity (< 1 mΩ·cm) and good conductivity without any dopant. So, we applied to the gate electrodes for organic thin film transistor (OTFTs). The conductive carbon film used as the electrodes has properties such as good adhesion to glass and plastic substrate, good physical properties for the lifetime of electrodes, good electrical properties, thermal stability and high transparency. In this work, we have fabricated organic thin film transistors (OTFTs) of a back gate structure using the pentacene active region on polyvinylphenol (PVP) as gate dielectric. We fabricated three different types of transistors using pentacene film grown on PVP gate dielectric with gate electrodes of N++Si, Au, and conductive carbon (a‐C) films. We investigated the current image property of two structures by using the SPM method and compared the topology with its current images, which were simultaneously obtained by scanning a 3 μm × 3 (m region. The current images of OTFT with the different gate electrodes have shown that the vertical leakage current flows along the pentacene grain edges. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Hot carrier effects in depletion-mode MOSFETs

Substrate current (I sub) due to the flow of hot holes from the drain depletion region of an n-channel depletion-mode transistor is measured. Three different types of transistors are fabricated by using various channel implantation doses with the same energy of implantation. A theoretical model is presented for I sub which agrees with the experimentally measured values. During gate current (I g) measurement, a change in polarity of the gate current due to channel hot carriers at a higher gate bias (V g) value is observed. At lower V g values the gate current is due to the flow of holes, and then electrons start flowing at higher V g values, which changes the I g polarity. It is observed that for high field effects the increase of drain bias has similar effects as a decrease of channel implantation dose required to fabricate the MOSFET.

A metallization system for microwave and UHF power transistors : L. W. Danley. Solid State Techn. June 1975. p. 35

The effects of gamma and neutron irradiations on two different types of transistors, Junction Field Effect Transistor (JFET) and Bipolar Junction Transistor (BJT), were investigated. Irradiation was performed using a Syrian research reactor (RR) (Miniature Neutron Source Reactor (MNSR)) and a gamma source (Co-60 cell). For RR irradiation, MCNP code was used to calculate the absorbed dose received by the transistors.The experimental results showed an overall decrease in the gain factors of the transistors after irradiation, and the JFETs were more resistant to the effects of radiation than BJTs. The effect of RR irradiation was also greater than that of gamma source for the same dose, which could be because neutrons could cause more damage than gamma irradiation.

Analysis of Transistor Failure in a Nuclear Environment

This paper describes a method for predicting transistor reliability as a function of nuclear radiation exposure, through the use of the Weibull distribution. Graphical plots of seven different types of transistors show ac gain degradation as a function of integrated neutron exposure. The plots on Weibull graph paper are extended to include probability of failure to 0.1 and 0.01 percent. The graphs are interpreted and the plotting technique and assumptions for extrapolation of the Weibull distribution are discussed.