HfO2 Dielectrics Research Articles

Numerical simulation of core shell dual metal gate stack junctionless accumulation mode nanowire FET (CS-DM-GS-JAMNWFET) for low power digital applications

In this paper, Core Shell Dual Metal Gate Stack Junctionless Accumulation Mode Nanowire FET (CS-DM-GS-JAMNWFET) is proposed, which has enhanced performance and is suitable for analog and digital applications. A high-k gate stack engineering, Hafnium Oxide (HfO2) is deployed in the outer as well as inner gate oxides of the core shell structure. The proposed device is compared with CS-DM-JAMNWFET, CS-SM-JAMNWFET, DM-GS-JAMNWFET, DM-JAMNWFET, and SM-JAMNWFET by maintaining a constant threshold voltage for all structures. The proposed CS-DM-GS-JAMNWFET provides a substantial reduction in subthreshold current with a high Ion/Ioff ratio as compared to other competent device structures. Also, the proposed device exhibits improvements in various parameters compared to the SM-JAMNWFET. It shows improvement in drain current (2.27 times), output conductance (2.14 times), subthreshold swing (0.94 times), transconductance (2.47 times), gate capacitance (2.00 times), cut-off frequency (1.24 times), intrinsic gain (12.95 times), current gain (1.46), Ion/Ioff ratio (6.15 times), unilateral power gain (1.09 times), maximum transducer power gain (1.08 times), Transconductance Generation factor (1.08 times), gain frequency product (14.61 times), transconductance frequency product (1.32 times), and gain transconductance frequency product (17.27 times). These benefits are due to combined advantages of the dual metal high-k dielectric HfO2 structure in core shell JAM FET, which enhances the device's gate dominance over the channel with high driving current.

Realization of Extremely High-Gain and Low-Power in nMOS Inverter Based on Monolayer WS2 Transistor Operating in Subthreshold Regime.

In this work, we report an n-type metal-oxide-semiconductor (nMOS) inverter using chemical vapor deposition (CVD)-grown monolayer WS2 field-effect transistors (FETs). Our large-area CVD-grown monolayer WS2 FETs exhibit outstanding electrical properties including a high on/off ratio, small subthreshold swing, and excellent drain-induced barrier lowering. These are achieved by n-type doping using AlOx/Al2O3 and a double-gate structure employing high-k dielectric HfO2. Due to the superior subthreshold characteristics, monolayer WS2 FETs show high transconductance and high output resistance in the subthreshold regime, resulting in significantly higher intrinsic gain compared to conventional Si MOSFETs. Therefore, we successfully realize subthreshold operating monolayer WS2 nMOS inverters with extremely high gains of 564 and 2056 at supply voltage (VDD) of 1 and 2 V, respectively, and low power consumption of ∼2.3 pW·μm-1 at VDD = 1 V. In addition, the monolayer WS2 nMOS inverter is further expanded to the demonstration of logic circuits such as AND, OR, NAND, NOR logic gates, and SRAM. These findings suggest the potential of monolayer WS2 for high-gain and low-power logic circuits and validate the practical application in large areas.

Design and Comparative Analysis of Ferroelectric Nanowire with Dielectric HfO2 and Al2O3 for Low-Power Applications

Design and Comparative Analysis of Ferroelectric Nanowire with Dielectric HfO2 and Al2O3 for Low-Power Applications

Polymer nanocomposites with concurrently enhanced dielectric constant and breakdown strength at high temperature enabled by rationally designed core-shell structured nanofillers

Polymer dielectrics are required to maintain high energy density at elevated temperatures for advanced power and electronic systems. Herein, we report a novel solution-processed core-shell structured polyimide (PI) nanocomposite with moderate dielectric constant HfO2 core and wide-bandgap Al2O3 shell, effectively addressing the typical trade-off between dielectric constant and breakdown strength in dielectric nanocomposites predominant at elevated temperatures. The formation of improved dielectrically matching interfaces by the rationally designed dielectric constant gradient from core-shell-matrix remarkably mitigates the distortion of the electric field around the interfaces, resulting in a high breakdown strength. Wide band gap Al2O3 shell also introduces deeper traps to impede the conduction loss. The validity of Al2O3 shell has been proved via experiments and simulations. Accordingly, HfO2@Al2O3/PI nanocomposite exhibits an excellent charge-discharge efficiency of 91.7 % at 300 MV/m and a maximum discharged energy density of 2.94 J/cm3 at 150 °C, demonstrating its potential for high-temperature energy storage.

Mole Fraction and Device Reliability Analysis of Vertical-Tunneling-Attributed Dual-Material Double-Gate Heterojunction-TFET with Si0.7Ge0.3 Source Region at Device and Circuit Level

This paper puts forward a new vertical-tunneling-attributed dual-material double-gate heterojunction-TFET (VTDMDG-HTFET). The device structure of VTDMDG-HTFET includes Si[Formula: see text]Ge[Formula: see text] material for the designing of source region. The mechanism of vertical tunneling in VTDMDG-HTFET provides superior electric field at tunneling interface and leads to improved transfer characteristics. VTDMDG-HTFET also includes metal gate work-function engineering approach to facilitate high ON-current and small OFF-current. Application of high-[Formula: see text] dielectric material HfO2 in the form of gate oxide enhances the capacitive-coupling at channel-source interface. Moreover, the work includes the comparison of proposed VTDMDG-HTFET with the conventional vertical-tunneling based dual-material double-gate-TFET (VTDMDG-TFET). It has been observed from the simulation results that SiGe source-based VTDMDG-HTFET offers better DC characteristics in terms of superior ON-current, smaller OFF-current, steeper subthreshold-slope, lower threshold voltage, higher transconductance along with smaller drain-induced barrier-lowering (DIBL) effects as compared to its counterpart silicon-source-based VTDMDG-TFET. In this work, reliability of VTDMDG-HTFET has also been examined and compared with VTDMDG-TFET in terms of temperature sensitivity and effect of different interface trap charges. The device simulation and investigations have been carried out using technology computer aided design (TCAD) tool. Moreover, device circuit mixed-mode simulation analysis is carried out for conventional and proposed device based resistive load inverters. A comparison is performed between both the inverters in terms of prorogation delay and switching threshold voltages. Further, the mixed mode simulation analysis is also performed for the proposed device based inverter under the influence of different interface trap charges (ITCs). Study shows that reliability performance of the proposed device is better as compared to its counterpart conventional device. Hence, vertical tunneling and SiGe source-based VTDMDG-HTFET can be a better choice for various applications such as analog/RF, analog and digital electronic circuits, energy harvesting, gas-sensing and memory devices.

Synthesis of Dielectric Al-Doped HfO2 Thin Film by Polymer-Assisted Deposition

As transistors scale down, demands for high-k dielectric materials increase. Among various dielectric materials, HfO2 have drawn attention because of its large band gap, high dielectric constant, and excellent physical/chemical stability. Although several solution-based synthesis have been developed, their dielectric properties are inferior to those obtained by conventional vacuum processes (e.g., atomic layer deposition, sputtering). This study demonstrates a solution-based polymer-assisted deposition (PAD) of high-k Al-doped HfO2 thin films exhibiting excellent dielectric properties comparable to the conventional deposition methods. The PAD process enables the control of film thickness (≥3 nm) and the homogenous Al doping in the entire thin film. The key to the success is HCl-mediated coordination of metal ions and polymer. Systematic analysis on the structure and chemical composition of the dielectric layer is carried out. It is found that the phase transition from monoclinic phase to a mixture of tetragonal and amorphous phases results in excellent dielectric properties. The 7.8 nm thick thin film doped with 4.1 at% of Al exhibits a high dielectric constant of 30.2 with a high areal capacitance (674 nF cm−2 at 1.0 kHz), a low leakage current (3.3 × 10−9 A cm−2 at 2.0 MV cm−1), and a high breakdown voltage (7.7 V).

Effect of high-k dielectric HfO2 on performance of AlGaN/GaN based MOSHEMT for RF applications

Effect of high-k dielectric HfO2 on performance of AlGaN/GaN based MOSHEMT for RF applications

Optimal Coatings of Co3O4 Anodes for Acidic Water Electrooxidation.

Implementation of proton-exchange membrane water electrolyzers for large-scale sustainable hydrogen production requires the replacement of scarce noble-metal anode electrocatalysts with low-cost alternatives. However, such earth-abundant materials often exhibit inadequate stability and/or catalytic activity at low pH, especially at high rates of the anodic oxygen evolution reaction (OER). Here, the authors explore the influence of a dielectric nanoscale-thin oxide layer, namely Al2O3, SiO2, TiO2, SnO2, and HfO2, prepared by atomic layer deposition, on the stability and catalytic activity of low-cost and active but insufficiently stable Co3O4 anodes. It is demonstrated that the ALD layers improve both the stability and activity of Co3O4 following the order of HfO2 > SnO2 > TiO2 > Al2O3, SiO2. An optimal HfO2 layer thickness of 12nm enhances the Co3O4 anode durability by more than threefold, achieving over 42h of continuous electrolysis at 10mA cm-2 in 1m H2SO4 electrolyte. Density functional theory is used to investigate the superior performance of HfO2, revealing a major role of the HfO2|Co3O4 interlayer forces in the stabilization mechanism. These insights offer a potential strategy to engineer earth-abundant materials for low-pH OER catalysts with improved performance from earth-abundant materials for efficient hydrogen production.

Gate-mesa trench enables enhanced β-Ga2O3 MOSFET with higher power figure of merit

In this article, a gate-mesa trench (GMT) β-Ga2O3 metal-oxide-semiconductor field-effect transistor (MOSFET) device with enhanced performance and breakdown voltage improvement is proposed. Compared with the gate-field plate trench (GFPT), the breakdown voltage and power figure of merit (PFOM) of the GMT device are 2566 V and 680.53 MW cm−2 respectively, which are 1.56 times and 2.25 times higher than those of the GFPT, demonstrating excellent device performance. When the etch depth is 200 nm, the specific on-resistance of the GFPT and the GMT is 8.84 mΩ cm−2 and 9.76 mΩ cm−2, respectively, with the peak transconductance of the GFPT being 61.56 mS mm−1 when the epitaxial layer doping concentration is 3 × 1017 cm-3, which is 1.22 times that of the GMT. The high dielectric constant HfO2 dielectric can significantly improve the PFOM of the device, while the gate oxide Al2O3 drifts the threshold voltage to the right. This article presents a novel approach for designing high-performance enhanced β-Ga2O3 MOSFETs.

Effects of stacking sequence and top electrode configuration on switching behaviors in ZnO-HfO2 hybrid resistive memories

The resistive switching (RS) behavior of multilayered ReRAM devices is typically influenced by two aspects: the intrinsic properties of the dielectric multilayer, and other extrinsic contributions. In this study, we deposited and investigated bi-layered memories incorporating ZnO and HfO2 dielectrics. Different stacking sequences of the two oxides (ZnO/HfO2 and HfO2/ZnO) were employed to explore the intrinsic contribution of the bilayer microstructure, while different top electrode configurations (Pt and Ti) were utilized to demonstrate the extrinsic impact. All devices exhibit characteristic bipolar RS behavior, showcasing their functionality. But interestingly, the device with a Pt top electrode displays digital RS behavior, while the one with a Ti top electrode exhibits analog RS behavior. The completely different switching types observed during the reset process of the ZnO-HfO2 hybrid resistive memories are attributed to different interface charge migration process and structural characteristic. And as compared to the tailoring effect of stacking sequences (bilayer microstructure and oxide/oxide interface), the tailoring effect of top electrode configuration (electrode materials and oxide/electrode interface) is much stronger. Based on the latter, the switching ratio can be remarkably improved by at least two orders of magnitude, the reset voltage (energy consumption) can also be significantly reduced, and other discussed switching parameters can also show greater improvement. The comprehensive comparative analysis of intrinsic and extrinsic contributions provides valuable insights for exploring the RS mechanism and optimizing the design of bi-layered memory devices.

Performance and stability improvement of CVD monolayer MoS2 transistors through HfO2 dielectrics engineering

Monolayer molybdenum disulfide (MoS2) is a promising semiconductor channel material for future electronics due to its atomic thickness and high mobility. However, conventional back-gate MoS2 transistors suffer from substantial scattering caused by substrate and surface adsorbates, which impair carrier mobility and device reliability. In this work, we demonstrate an exemplary dielectric engineering approach that uses atomic-layer-deposited hafnium oxide (HfO2) as the gate dielectric and channel passivation layer to improve device performance and positive bias instability. The large-single-crystal monolayer MoS2 film was directly synthesized on SiO2/Si substrates by a low-pressure chemical vapor deposition method. MoS2 transistors with various dielectrics were fabricated and characterized for a fair comparison. The mobility increased from 4.2 to 19.9 cm2/V·s by suppressing charged impurities and phonon scattering when transferring the MoS2 channel from 100 nm SiO2 substrates to 20 nm HfO2 substrates. Passivation of another 10 nm HfO2 on the back-gate transistors further increased the mobility to 36.4 cm2/V·s with a high drive current of 107 μA/μm. Moreover, the threshold voltage shift of the passivated transistor was reduced by about 58% from 1.9 to 0.8 V under positive bias stress. This is due to the fact that channel passivation with HfO2 effectively eliminated charge trapping of adsorbed substances. These results reveal that HfO2 gate dielectric and passivation by atomic-layer deposition are effective methods to improve the performance and stability of MoS2 devices.

Simultaneously-doping of HfO2 thin films by Ni with sputtering technique and effect of post annealing on structural and electrical properties

This article reports a detailed structural and electrical characterization study of Ni:HfO2 dielectrics grown by rf and dc sputtering and variations in the rapid thermal annealing temperature. Annealing produced obvious changes in the morphological structure of films and XRD confirmed that the crystallite size increased from 1.3 nm to 14.4 nm with the annealing temperature. XPS showed that the amount of non-lattice oxygen decreased owing to the effects of annealing and resistivity. Dc resistivity measurements showed that the lowest sheet resistance of 1.182 × 106 Ω/□ was achieved by as-deposited films and increased to 70.960 Ω/□ with annealing. Structural differences in films due to the effect of annealing caused equivalent circuit models to vary and different resistance values in electrochemical impedance spectrometry. This study illustrates that HfO2 thin films, boosted by doping and rapid thermal annealing, provide a route toward advanced gate oxide stack structures in electronic devices beyond conventional high-dielectric-constant materials.

Wafer-scale high-κ dielectrics for two-dimensional circuits via van der Waals integration

The practical application of two-dimensional (2D) semiconductors for high-performance electronics requires the integration with large-scale and high-quality dielectrics—which however have been challenging to deposit to date, owing to their dangling-bonds-free surface. Here, we report a dry dielectric integration strategy that enables the transfer of wafer-scale and high-κ dielectrics on top of 2D semiconductors. By utilizing an ultra-thin buffer layer, sub-3 nm thin Al2O3 or HfO2 dielectrics could be pre-deposited and then mechanically dry-transferred on top of MoS2 monolayers. The transferred ultra-thin dielectric film could retain wafer-scale flatness and uniformity without any cracks, demonstrating a capacitance up to 2.8 μF/cm2, equivalent oxide thickness down to 1.2 nm, and leakage currents of ~10−7 A/cm2. The fabricated top-gate MoS2 transistors showed intrinsic properties without doping effects, exhibiting on-off ratios of ~107, subthreshold swing down to 68 mV/dec, and lowest interface states of 7.6×109 cm−2 eV−1. We also show that the scalable top-gate arrays can be used to construct functional logic gates. Our study provides a feasible route towards the vdW integration of high-κ dielectric films using an industry-compatible ALD process with well-controlled thickness, uniformity and scalability.

Nanostructures Stacked on Hafnium Oxide Films Interfacing Graphene and Silicon Oxide Layers as Resistive Switching Media.

SiO2 films were grown to thicknesses below 15 nm by ozone-assisted atomic layer deposition. The graphene was a chemical vapor deposited on copper foil and transferred wet-chemically to the SiO2 films. On the top of the graphene layer, either continuous HfO2 or SiO2 films were grown by plasma-assisted atomic layer deposition or by electron beam evaporation, respectively. Micro-Raman spectroscopy confirmed the integrity of the graphene after the deposition processes of both the HfO2 and SiO2. Stacked nanostructures with graphene layers intermediating the SiO2 and either the SiO2 or HfO2 insulator layers were devised as the resistive switching media between the top Ti and bottom TiN electrodes. The behavior of the devices was studied comparatively with and without graphene interlayers. The switching processes were attained in the devices supplied with graphene interlayers, whereas in the media consisting of the SiO2-HfO2 double layers only, the switching effect was not observed. In addition, the endurance characteristics were improved after the insertion of graphene between the wide band gap dielectric layers. Pre-annealing the Si/TiN/SiO2 substrates before transferring the graphene further improved the performance.

A Gate-All-Around inO Nanoribbon FET With Near 20 mA/m Drain Current

In this work, we demonstrate atomic-layer-deposited (ALD) single-channel indium oxide (In2O3) gate-all-around (GAA) nanoribbon FETs in a back-end-of-line (BEOL) compatible process. A maximum on-state current (ION) of 19.3 mA/{\mu}m (near 20 mA/{\mu}m) is achieved in an In2O3 GAA nanoribbon FET with a channel thickness (TIO) of 3.1 nm, channel length (Lch) of 40 nm, channel width (Wch) of 30 nm and dielectric HfO2 of 5 nm. The record high drain current obtained from an In2O3 FET is about one order of magnitude higher than any conventional single-channel semiconductor FETs. This extraordinary drain current and its related on-state performance demonstrate ALD In2O3 is a promising oxide semiconductor channel with great opportunities in BEOL compatible monolithic 3D integration.

(Invited) Vertical Transparent ZnO TFT Based on a Stack of Thin-Films Deposited in Solution

A lot of works are devoted now to integrate driving TFT with OLED, minimizing the area of the pixel. In other part, people try to fabricate devices using low cost technologies as deposition in solution avoiding any photolithography step in the process. Finally, it can be better if the full driving TFT-OLED device is transparent.The present work try to answer simultaneously to these 3 desires. Particularly, the present paper focus on the TFT.Vertical TFT will answer to the first desire to minimize the area of the device. It is based here on a stack of the gate, the insulator, the source, the semiconducting active layer and the drain; meaning 5 films all solution deposited.Thanks to the present available insulator solutions for the deposition, different insulators can be chosen. High k HFO2 insulator is chosen in this work. It is is spincoated and then annealed at 300C during 1 hour. Figure 1 shows the current-voltage curves of ITO/HFO2/AgNWs stack. After rapid increase, the current stabilizes at 10 pAmp at least still a voltage of 10V, meaning a field of 7.7x105 V/cm2 with a thickness of 130 nm. Present HFO2 film is then a good insulator.ZnO is chosen as active layer. It is spin-coated and then annealed at 180C. This temperature was found enough high to lower the conductivity (Figure 2)The source and drain layers are spin-coated using Ag nanowires (AgNWs) solution. As source AgNWs layer is deposited before ZnO layer, it will be annealed at the same temperature 180C. Figure 3 shows that AgNWs film stays enough conducting after such annealing temperature. It can be used as conducting source and drain.Finally, the full stack of 5 films is characterized as a TFT.Figure 4 shows the transfer characteristic of this TFT plotted at a drain voltage of 2.6V. The drain current is modulated by 4 orders from off to on regime.Very simple and low cost fully in solution process is presented in this work. Working transparent TFT is demonstrated. The process shows its high potential in the development of integrated TFT-OLED in small area. It is very promising.Its shows also the need of future hard work in this way to demonstrate fully integrated driving TFT-OLED Figure 1

Artificially induced ferroelectric-like behavior in an antiferroelectric sandwich structure by interface engineering

Interface engineering is essential for achieving fascinating interfacial functionalities in a single all-oxide-interface-based device. In the present work, a sandwich structure (Pb0.94La0.06(Zr0.95Ti0.05)O3 (PLZT)/HfO2/ Pb0.94La0.06(Zr0.95Ti0.05)O3) was fabricated via a chemical solution approach. A distinct “ferroelectricity-like” behavior with high Pmax (∼ 80 μC/cm2) and Pr (∼ 36 μC/cm2) is demonstrated. The dielectric HfO2 thin layer presents a tetragonal symmetry structure, which stabilizes a slight distorted structure of the upper PLZT layer (PLZT(T)) with a= 4.19(9) Å, b= 4.10(6) Å, β ∼ 91.04˚. In PLZT(T), the ferroelectric (FE) phase is identified as the matrix embedded with a small amount of AFE nanodomains, while the bottom PLZT layer (PLZT(B)) exhibits typical AFE incommensurately modulated structures. The near-interface structures in both PLZT layers are characterized by ferroelectric polarizations with head-to-tail configuration across the heterointerface. Such discontinuous, downward polarizations support the accumulation of oxygen vacancies at the heterointerface that facilitate the local polarization enhancement. It is the combination effect of stable ferroelectric polarization in the PLZT(T) layer, interfacial oxygen vacancies and large surface to volume ratio that leads to the superior polarization performance of the antiferroelectric sandwich structure. It indicates that interface engineering is a feasible approach to manipulate the ferroic behavior.

Drain-extended MOS design using High-k dielectric to control off-state BTBT with enhanced switching performance

This work explores the application of high-k dielectric to suppress off-state band-to-band tunneling (BTBT) and enhance the switching performance of conventional Drain-extended NMOS (C_DeNMOS). C_DeNMOS switching performance is limited by extended gate over the drift region, while the high field effects near the gate edge are responsible for BTBT below the gate-to-drain overlap region. We investigate two improved configurations of DeNMOS (1) Planar and (2) Trench structures incorporating a floating plate (FP). In comparison to C_DeNMOS, it is demonstrated that employing high-k dielectric HfO2 with appropriately doped FP in the Planar and Trench structures can efficiently modulate the surface field while also reducing surface charge accumulation. As a result, BTBT is suppressed in Planar and Trench structures when HfO2 is used as dielectric, in addition to improvement in switching delay, reverse recovery behavior, and switching energy performance at higher operating frequencies.

Dielectric breakdown in HfO2 dielectrics: Using multiscale modeling to identify the critical physical processes involved in oxide degradation

We use a multi-scale modeling to study the time-dependent dielectric breakdown of an amorphous (a-) HfO2 insulator in a metal–oxide–metal capacitor. We focus on the role played by electron injection in the creation of oxygen vacancies, which eventually form the percolation path responsible for dielectric breakdown. In this scenario, the electron transport through the dielectric occurs by multi-phonon trap assisted tunnelling (MPTAT) between O vacancies. Energy parameters characterizing the creation of oxygen vacancies and the MPTAT process are calculated using density functional theory employing a hybrid density functional. The results demonstrate that the formation of neutral O vacancies facilitated by electron injection into the oxide represents a crucial step in the degradation process dominating the kinetics at common breakdown fields. We further show the importance of the so-called “energetic correlation” effect, where pre-existing O vacancies locally increase the generation rate of additional vacancies accelerating the oxide degradation process. This model gives realistic breakdown times and Weibull slopes and provides a detailed insight into the mechanism of dielectric breakdown and atomistic and electronic structures of percolation paths in a-HfO2. It offers a new understanding of degradation mechanisms in oxides used in the current MOSFET technology and can be useful for developing future resistive switching and neuromorphic nanodevices.

Multi-Layer High-K Gate Stack Materials for Low D<sub>it</sub> 4H-SiC Based MOSFETs

Metal-oxide-semiconductor capacitors with single and multi-layer high-K gate dielectrics on Si (0001) face of n-type 4H-SiC substrates have been investigated. Multi-layered nanolaminated gate-stack comprises alternating ultrathin (6nm) Al2O3 and HfO2. A 5nm thick interfacial silicon oxynitride is deposited prior to laminated films to investigate interface trap properties and tuning of flat band voltage. Total thickness of gate-stack films including interfacial layer is 55nm. The thermal stability of multi-layered nanolaminated film is investigated using XTEM. Localized crystallization of HfO2 is visible after RTA at 900°C while Al2O3 remains fully amorphous. Some of HfO2 grains have extended into Al2O3 layer but was not able to crossover. The measured accumulation capacitance of 55nm thick gate dielectric gives an effective dielectric constant value of 9.6 and an equivalent oxide thickness of 22nm from high-frequency capacitance-voltage measurements. A positive flat band voltage ( of 12.2V and 10.6V are observed from both single layer HfO2 and Al2O3 dielectrics, respectively due to presence of negatively charged oxygen interstitial defects generated during atomic layer deposition process. However, VFB shifted towards negative voltage-7.6V for multi-layered Al2O3/HfO2 stacks probably associated with positive Al and Hf interstitials at interface of Al2O3/HfO2. Ultrathin interfacial oxynitride films is effective to reduce Dit to 3×1011/eVcm2 and tuning of VFB. The breakdown field of stacked gate dielectric on 4H-SiC is 10.0 MV/cm.