Multi-Layer High-K Gate Stack Materials for Low D<sub>it</sub> 4H-SiC Based MOSFETs

Abstract

Metal-oxide-semiconductor capacitors with single and multi-layer high-K gate dielectrics on Si (0001) face of n-type 4H-SiC substrates have been investigated. Multi-layered nanolaminated gate-stack comprises alternating ultrathin (6nm) Al2O3 and HfO2. A 5nm thick interfacial silicon oxynitride is deposited prior to laminated films to investigate interface trap properties and tuning of flat band voltage. Total thickness of gate-stack films including interfacial layer is 55nm. The thermal stability of multi-layered nanolaminated film is investigated using XTEM. Localized crystallization of HfO2 is visible after RTA at 900°C while Al2O3 remains fully amorphous. Some of HfO2 grains have extended into Al2O3 layer but was not able to crossover. The measured accumulation capacitance of 55nm thick gate dielectric gives an effective dielectric constant value of 9.6 and an equivalent oxide thickness of 22nm from high-frequency capacitance-voltage measurements. A positive flat band voltage ( of 12.2V and 10.6V are observed from both single layer HfO2 and Al2O3 dielectrics, respectively due to presence of negatively charged oxygen interstitial defects generated during atomic layer deposition process. However, VFB shifted towards negative voltage-7.6V for multi-layered Al2O3/HfO2 stacks probably associated with positive Al and Hf interstitials at interface of Al2O3/HfO2. Ultrathin interfacial oxynitride films is effective to reduce Dit to 3×1011/eVcm2 and tuning of VFB. The breakdown field of stacked gate dielectric on 4H-SiC is 10.0 MV/cm.