Dielectric Isolation Research Articles

Moore's Law Scaling and Chemical Mechanical Planarization (CMP)

Since the invention of the first integrated circuit in 1958, chemistry and materials have played a critical role in semiconductor process technologies, which has led to an exponential growth of transistors packed into circuits. Decades ago, Gordon Moore posited there would be a doubling of components every two years (revised from his original doubling every one-year prediction). This observation became known as Moore’s law.As Denard scaling took on more complexity, the number of new materials used to build semiconductors increased at a torrid pace. The number of elements in the periodic table, used to fabricate devices, increased roughly five-fold from the 1980’s to the 2000’s.In the earlier years, lithography, etch, thin films, implant, and diffusion were foundational technologies used to fabricate a silicon wafer into hundreds of microchips. In the late 1980’s a new technology Chemical Mechanical Planarization (CMP) was invented. It was developed out of necessity to reduce topography, critical for lithography’s depth of focus requirements. Without this key invention, patterning and building layer upon layer from front end transistors to back-end interconnects would not have been possible.Intel implemented CMP into manufacturing in the early 1990’s on the 0.8 micron technology node which manufactured the 486 microprocessor. CMP was required to planarize dielectric oxide used to insulate the aluminum metal interconnects. Since then, the number of CMP applications over the last three decades has exploded, enabling the scaling of Moore’s Law.CMP is not only used to improve lithography depth of focus. CMP also enables a method of metal interconnect and contact formation called damascene. Planarization is used to create dielectric isolation trenches, discrete plugs for insulation, aid advanced patterning architectures, build through silicon vias (TSVs), and enable complex wafer and chip bonding for die-to-die interconnects for disaggregated products.Transistor scaling alone is no longer sufficient to meet device performance, power, and cost requirements. Complex material and architectural changes are required. And novel CMP applications continue to be added at each new technology node. This author will make an argument that CMP is critical to push scaling and enable future process nodes. Figure 1

Radiation effects on multi-channel Forksheet-FET and Nanosheet-FET considering the bottom dielectric isolation scheme

This study analyzes the single-event transient (SET) characteristics of alpha particles on multi-channel Forksheet-FET and Nanosheet-FET at the device and circuit levels through 3D TCAD simulations. The study investigates the differences in SET responses based on the energy and incident position of incoming alpha particles, considering the structural variances between Forksheet-FET and Nanosheet-FET, as well as the presence or absence of bottom dielectric isolation (BDI) in the fabrication process. Specifically, the introduction of BDI is observed to significantly suppress the voltage drop caused by ‘unintended' current, as it can block the substantial electron-hole pairs (EHP) generated by injected alpha particles in the bulk substrate from reaching the FET terminals. Furthermore, it was confirmed that the size of abnormal current decreases as the energy of the injected alpha particle increases. Additionally, evaluating the response to SET based on the fundamental logic circuit, the CMOS inverter, revealed relatively small abnormal voltage drops for both Forksheet and Nanosheet when BDI was applied, confirming high immunity to radiation effects. Moreover, it can be observed that the application of BDI enhances reliability from a memory perspective by effectively suppressing voltage flips in the SRAM's cross-coupled latch circuit.

SiC-on-insulator based lateral power device and it’ s analytical models

This paper proposes the concept of SiC-on-insulator (SiCOI) lateral power device and its analytical models. The SiCOI technology provides dielectric isolation and improves the vertical breakdown. The analytical models provide the physic insight of the surface potential and electric field distributions for both full and partial depletion cases. The optimal breakdown voltage and doping concentration are deduced to analyze the breakdown mechanism qualitatively. The specific on-resistance in the drift region was also calculated to analyze the conduction characteristics. The influences of the structure parameters on the performances of the SiCOI lateral power device are investigated by the analytical model and numerical simulation. The analytical results of the proposed model are well agreement with the numerical results, confirming the validity of the proposed unified analytical model. Both the analytical and numerical results provide the physical explanation and effective solution for optimizing the electric field and improving breakdown voltage for the SiCOI lateral power device.

High-efficiency edge-emitting laser diodes with oxidation confinement stripe structure

High-efficiency, low-cost, high-power laser diodes (LDs) are in the spotlight due to the growing market demand. This study proposes a new edge-emitting LD structure that utilizes the facile oxidization properties of the high aluminum (Al) component AlGaAs material and simplifies LD fabrication to only one-step lithography. The key innovation is incorporating a ∼200 nm thick high-Al AlGaAs layer in the vertical epitaxial structure. This layer serves two purposes: 1) The low refractive index improves vertical mode confinement, enabling a thinner overall epitaxial structure. 2) Oxidation of this layer forms a dielectric isolator and a current aperture. Experimental LDs exhibited a peak efficiency of 77.8 %, peak power of 33.6 W, vertical divergence angle of 19.4°, and horizontal divergence angle of 8.8°. Compared to conventional edge-emitting LD, this LD demonstrates a 39 % lower thermal resistance, better optoelectronic performance, a simpler process, and a lower production cost.

Impact of Bottom Dielectric Isolation of Si-Stacked Nanosheet Transistor on Stress and Self-Heating at 3-nm Node and Beyond

Impact of Bottom Dielectric Isolation of Si-Stacked Nanosheet Transistor on Stress and Self-Heating at 3-nm Node and Beyond

A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors.

In this paper, a novel scheme for source/drain-first (S/D-first) full bottom dielectric isolation (BDI), i.e., Full BDI_Last, with integration of a sacrificial Si0.5Ge0.5 layer was proposed and demonstrated in a stacked Si nanosheet gate-all-around (NS-GAA) device structure using TCAD simulations. The proposed full BDI scheme flow is compatible with the main process flow of NS-GAA transistor fabrication and provides a large window for process fluctuations, such as the thickness of the S/D recess. It is an ingenious solution to insert the dielectric material under the source, drain and gate regions to remove the parasitic channel. Moreover, because the S/D-first scheme decreases the problem of high-quality S/D epitaxy, the innovative fabrication scheme introduces full BDI formation after S/D epitaxy to mitigate the difficulty of providing stress engineering in the full BDI formation before S/D epitaxy (Full BDI_First). The electrical performance of Full BDI_Last is demonstrated by a 4.78-fold increase in the drive current compared to Full BDI_First. Furthermore, compared to traditional punch through stoppers (PTSs), the proposed Full BDI_Last technology could potentially provide an improved short channel behavior and good immunity against parasitic gate capacitance in NS-GAA devices. For the assessed inverter ring oscillator (RO), applying the Full BDI_Last scheme allows the operating speed to be increased by 15.2% and 6.2% at the same power, or alternatively enables an 18.9% and 6.8% lower power consumption at the same speed compared with the PTS and Full BDI_First schemes, respectively. The observations confirm that the novel Full BDI_Last scheme incorporated into an NS-GAA device can be utilized to enable superior characteristics to benefit the performance of integrated circuits.

Coil High Voltage Spark Plug Boots Insulators Material Selection Using MCDM, Simulation, and Experimental Validation

The examination and choice of an alternate composite material for the high-voltage circuit of Otto cycle internal combustion engines—more commonly known as gasoline engines—are presented in the research that follows. To do this, multicriteria selection procedures are employed, and the outcomes are validated through the use of thermal character simulation software and standard laboratory tests. Nylon is the recommended material for Coils on Plug (COP) high-voltage insulators. Four of the six multicriteria selection techniques utilized in this study were found to be effective. It was discovered through the virtual simulation process that, even in the same environment with the same edge circumstances, the thermal behavior of the materials differs dramatically because the quadrants exhibit different behavior depending on the material. Given that nylon has a lower elasticity modulus than silicone, it was determined that the dimensions are crucial for the nylon Spark Plug Boot (SPB) to comply with the dielectric isolation process. It must have a minimal clearance in order to be related to the geometry of the spark plug and perform the perfect insulation in this manner.

Low temperature (<700 °C) SiO2 and Si-rich SiO2 films: Short review

SiO2 layers deposited at temperatures (lower than 700 °C) have attracted a great deal of attention for a large variety of applications, since they can be used for dielectric isolation, a needed approach for multilayer, multifunctional coatings that exhibit two or more properties simultaneously. A similar phenomenon occurred with Si-rich SiO2, a two-phase material in which excess silicon, introduced during the deposition process of the films, forms a Si inclusion phase uniformly embedded in a SiO2 matrix, modifying its optical and electrical characteristics. In this short review, the synthesis methods to obtain high electronic quality SiO2 deposited films at low temperatures, as well as Si-rich SiO2 films (mainly the chemical vapor deposition technique in different versions), precursor materials, and characteristic properties, will be described together with some of their applications, beyond integrated circuit technology, that have become relevant in recent times. This is the case of solar filters, antireflecting coatings for solar cell panels, light emitting devices or liquid crystal displays, and bioimaging and theranostic applications.

CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling

This article explores and evaluates six-transistor static random access memory (SRAM) bitcell design options for sequential and monolithic complementary field-effect transistors (CFET) in 5-Å-compatible (A5) and 3-Å-compatible (A3) technology. A5 CFET offers up to 55% and 40% SRAM bitcell area scaling due to stacked architecture as compared to 14-Å-compatible (A14) nanosheet (NS) technology and 10-Å-compatible (A10) forksheet (FS) technology counterparts, respectively. A dielectric isolation wall (DIW) between gates is introduced in A3 CFET SRAM as a scaling booster. Replacement of gate-cuts with DIW results in up to 17% bitcell area scaling in A3 as compared to A5 CFET SRAM. However, aggressive area scaling introduces routing complexity and limits the node-to-node power and performance (PP) gain. Thus, the interconnect design guidelines are provided to overcome these challenges for power, performance, and area (PPA) enhancements of high-density (HD) SRAM.

Study on low rate of change characteristics of saturation output current of 28 nm UTBB FDSOI at 300 °C high-temperature

Partially-depleted silicon-on-insulator (PDSOI) MOSFETs with full dielectric isolation structure are widely used in the high temperature field of 225 °C, but affected by the threshold voltage and carrier mobility, the saturated output current has a rate of change as high as 24.9% at 25 °C–300 °C, which will reduce the working speed and accuracy of the analog circuit. This paper studies the high temperature output current characteristics of ultra-thin body and buried oxide (UTBB) fully-depleted silicon-on-insulator (FDSOI) MOSFETs with the 28 nm low voltage threshold structure. The experimental results show that when the gate voltage of the device is constant, the saturation current change of 28 nm short-channel FDSOI device is 1.93% in the temperature range from 25 °C to 300 °C, which is 12.9 times more stable than that of 0.13 μm PDSOI device, 4.5 times and 8.4 times higher than that of 0.3 μm and 2 μm long-channel FDSOI device. When the gate voltage of the device drifts from the zero-temperature coefficient (ZTC) point by ±10%–±20%, the output current change of the short-channel FDSOI device is still the lowest. It is proved by theory and simulation that the low temperature change rate of the carrier velocity of the short-channel FDSOI device is the main factor affecting the stability of the output current. From the analysis of the saturation current model and the ZTC operating point, reducing the gate operating voltage of the device or increasing the threshold voltage of the device can further improve the stability of the output current at high temperatures. The research in this paper proves that the 28 nm UTBB FDSOI device has good high temperature saturation current stability, which can well meet the output current stability requirements of high temperature analog circuits.

A Review of the Gate-All-Around Nanosheet FET Process Opportunities

In this paper, the innovations in device design of the gate-all-around (GAA) nanosheet FET are reviewed. These innovations span enablement of multiple threshold voltages and bottom dielectric isolation in addition to impact of channel geometry on the overall device performance. Current scaling challenges for GAA nanosheet FETs are reviewed and discussed. Finally, an analysis of future innovations required to continue scaling nanosheet FETs and future technologies is discussed.

(Digital Presentation) Selective SiGe Vapor Etching Using Br2 in View of Nanosheet Device Isolation

Forksheet transistors are lateral nanosheet devices with a forked gate structure [1,2]. The physical separation of N- and PFETs by a dielectric wall enables N-P space scaling and consequently sheet width maximization within the limited footprint of low-track-height standard cells. Bottom dielectric isolation has been proposed to circumvent the junction isolation trade-off between punch-through suppression on the one hand and junction leakage and capacitance on the other hand [3]. A typical fabrication scheme includes the epitaxial growth of Si/Si1-yGey/multi-{Si1-xGex/Si} epi stacks (y>x) where the bottom Si1-yGey layer is later replaced by a SiN/SiCO isolation [4]. The fabrication scheme relies on selective etching of the sacrificial Si1-yGey layer with respect to the {Si1-xGex/Si} multi-stack. Owing to the very small dimensions (e.g. sub-10 nm nanowire channel diameter), high etch selectivity towards both Si1-xGex and Si, and excellent process controls are mandatory. This sets stringent requirements on the epitaxial stacks (thicknesses and composition control, sharpness of interfaces, and absence of strain relaxation) [4] as well as on the etch process itself (high selectivity, limited Si1-xGex and Si consumption) [5-7].The selective Si1-yGey removal requires a great precision in its adjustment, with the risk of experiencing process variabilities and yield issues. Selective SiGe etching is typically done in advanced wet or dry chemistries and is sensitive to both strain in and oxidation of individual layers [4-6]. Also, HCl-based vapor etching has been reported for SiGe removal, with high selectivity towards Si [7]. The HCl vapor etching requires a sufficiently high process temperature (typically ≥ 600°C). This makes it less attractive for fabrication schemes with bottom isolations. The presence of the Ge-rich Si1-yGey layer in the as-grown epi stack results in an enhanced risk for unwanted layer relaxation.A low temperature Br2-based vapor etching process is proposed as an alternative for the selective Si1-yGey removal in the isolation fabrication. After initial process screening on blanket epi layers to compare etching behavior for different process gases as function of material composition and crystallinity, it is demonstrated on patterned test structures that Br2 etching enables high etch selectivity of Si0.5Ge0.5 towards Si and Si1-xGex (x=0.2, 0.23, and 0.3).Figure 1 compares the etching characteristics of HCl, HBr, and Br2 as obtained for blanket Si1-xGex layers where the Ge content was varied between 0.2 and 0.5. In all cases, the etching is kinetically controlled. The etching rates indeed show a clear exponential dependence as function of the process temperature. While the etching rates are similar for HCl and HBr, the Arrhenius plot is shifted to ~300°C lower temperatures for Si1-xGex etching with Br2. For each process gas, the etching rate increases with increasing Ge concentration. This difference in etching rate as function of layer composition is highest for Br2. Figure 2 reports the obtained etching selectivity between Si0.5Ge0.5 and Si1-xGex (x = 0.15 – 0.36) as obtained for Br2 etching on blanket wafers. Selective etch tests with Br2 as etching gas were conducted on fin patterned structures consisting of Si-substrate / 10 nm Si0.5Ge0.5 / 3x {9 nm Si1-xGex / 9 nm Si}. Different etching times have been applied to demonstrate the concept and to validate etch selectivity between Si0.5Ge0.5 and Si1-xGex/Si. Figure 3 displays low magnification X-TEM images of the structure with x=0.2, after fin patterning, 1 min, and 3 min Br2 etching. The selective etching of the Si0.5Ge0.5 layer is clearly demonstrated, although the shortest etching time is not sufficient for complete Si0.5Ge0.5 removal while the sample etched for 3 min was clearly over etched. Lateral material loss of the upper two Si0.8Ge0.2 layers is limited to 2-3 nm (Fig. 3b) and 3-4 nm (Fig. 3c), respectively. During lateral Si0.5Ge0.5 etching, the lowest Si0.8Ge0.2 layer gets exposed to the Br2 etching gas both from the side walls as well as from the bottom surface. The severe etching of this layer is also observed for other etching routines and can easily be avoided by adding a thin Si layer between the Si0.5Ge0.5 layer and the first Si0.8Ge0.2 layer.

(Digital Presentation) Selective SiGe Vapor Etching Using Br2 in View of Nanosheet Device Isolation

Both forksheet and CFET device layouts contain local dielectric isolation layers to circumvent junction isolation trade-offs which are specific for these designs. Typical fabrication schemes start with the epitaxial growth of complicated SiGe/Si multi stacks with at least two different Ge concentrations where a Ge-rich SiGe layer is later replaced by an isolating dielectric. This work proposes a low temperature Br2-based vapor etching process as an option for the selective SiGe removal in the isolation fabrication. After initial process screening on blanket epi layers to compare etching behavior for different process gases as function of material composition and crystallinity, it is demonstrated on patterned test structures that Br2 etching enables high etching selectivity of Si0.5Ge0.5 towards Si and Si1-xGex (x = 0.2 - 0.3).

Exploration on Electrical Isolation Between High-Voltage SiC Thyristor and Small-Signal Devices for Smart Power Devices

The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Smart Discrete</i> concept which monolithically integrates a vertical high-voltage power device with low-voltage smart circuits has been widely adopted in silicon world for many years and may bring similar benefits to SiC world. For example, it is highly desirable to integrate a gate driver circuit onto a high-voltage SiC thyristor for ultra-fast turn-on. However, the electrical isolation between the vertical high-voltage power device and the low-voltage circuit elements remains a major technical challenge for silicon, and even more so for SiC due to the very limited processing options. In this article, we propose a combination of shallow junction isolation (JI) and partial dielectric isolation (DI) for high-voltage 4H-SiC smart thyristor, which is monolithically integrated with low-voltage nMESFET circuits. The characterization of fabricated devices and analysis of leakage currents across the isolation structure have been done to experimentally verify the feasibility of the isolation method. 8 V parasitic lateral NPNP thyristor between a 6.3 kV 4H-SiC thyristor and isolation moats, 175 V lateral PNP transistor between the passive resistor and isolation moats, and 10 V lateral reverse-biased p-n diode between nMESFET and isolation moats are experimentally demonstrated.

Dielectric engineering for improvement of mobility and photoelectric performance in 2D BiI3

Two-dimensional (2D) bismuth triiodide (BiI3) has been emerging as a potential layered material for optoelectronic applications due to its air stability and high atomic density. Although much effort has been devoted to improvements of carrier mobility, conductivity and photoelectric response, performance is still very limited. Here, we report a simple and scalable strategy for greatly improving the electrical and optical properties of 2D BiI3 through high-κ dielectric engineering. Upon covering with a high-κ dielectric oxide (Al2O3), air isolation and dielectric screening effects can lead to the reduction of the contact barrier, passivation of trap states, and suppression of Coulomb scattering. As a result, BiI3-based phototransistors can increase carrier mobility by three orders of magnitude and improve photoresponsivity by three orders of magnitude up to 8.05 × 103 A W−1. This work develops a new 2D BiI3 material and efficient dielectric engineering for improving mobility and photoelectrical performance, expanding the family of 2D materials and offering a promising strategy for potential nano-device applications.

Rational Design and Numerical Analysis of a Hybrid Floating cIDE Separator for Continuous Dielectrophoretic Separation of Microparticles at High Throughput.

Dielectrophoresis (DEP) enables continuous and label-free separation of (bio)microparticles with high sensitivity and selectivity, whereas the low throughput issue greatly confines its clinical application. Herein, we report a novel design of the DEP separator embedded with cylindrical interdigitated electrodes that incorporate hybrid floating electrode layout for (bio)microparticle separation at favorable throughput. To better predict microparticle trajectory in the scaled-up DEP platform, a theoretical model based on coupling of electrostatic, fluid and temperature fields is established, in which the effects of Joule heating-induced electrothermal and buoyancy flows on particles are considered. Size-based fractionation of polystyrene microspheres and dielectric properties-based isolation of MDA-MB-231 from blood cells are numerically realized, respectively, by the proposed separator with sample throughputs up to 2.6 mL/min. Notably, the induced flows can promote DEP discrimination of heterogeneous cells. This work provides a reference on tailoring design of enlarged DEP platforms for highly efficient separation of (bio)samples at high throughput.

Design and Fabrication of Leadless Package Structure for Pressure Sensors

Abstract Silicon piezoresistive pressure sensors can only operate below 125 °C due to the leakage current of the PN junction. However, silicon-on-insulator (SOI) high-temperature pressure sensors use SiO2 for total dielectric isolation to solve this problem. At present, SOI high-temperature pressure sensors mostly use lead bonding package structure, with gold wire to lead the electrical signal and silicone oil as the protection medium, but the working temperature of silicone oil is limited to about 150 °C. In this paper, the leadless package structure is designed using pressure conduction on the backside of the chip and replacing the gold wire with sintered silver paste. The materials and dimensions of the leadless package structure are determined and then obtained a complete package structure through manufacturing. The reliability of the leadless package structure after silver paste sintering was verified by finite element analysis, and the results showed that the thermal stress caused by high and low-temperature cycles in the leadless package is minimal and does not affect the sensitivity of the pressure-sensitive chip. The size of the leadless package structure was optimized by Taguchi orthogonal method, and the maximum thermal stress was effectively reduced. Also, the key factors affecting the thermal stress of the leadless package in the package structure were identified by the variance number analysis method. The optimized leadless package structure size was remanufactured, and the sintered package structure was tested. The data show that the sensitivity of the pressure sensor is 30.82 mV/MPa with a nonlinearity of less than 0.4% full-scale (FS).

Time dependence of the concentration of dissolved ozone in water generated by dielectric barrier discharge (DBD) plasma using atmospheric air

Ozone is one of the reactive oxygen species that can be produced from plasma. In this study, the ozone was generated by using a dielectric barrier discharge (DBD) plasma technology. DBD plasma was generated using two electrodes separated by a glass dielectric isolator and an alternating current (AC) voltage source of 5 kV with an airflow rate of 1 L/min at room temperature and atmospheric pressure. In this study, the ozone concentration was determined using the titration method. The ozone concentration was measured by varying the titration time between 0-10 minutes. The time dependence of ozone concentration in water tends to follow the polynomial trendline. The longer plasma treatment was performed, the higher ozone concentration was measured. The ozone significantly increased when the treatment was conducted for more than 6 min.

A Frequency-Selective Surface Rasorber Based on Four Functional Layers

In this article, a frequency-selective surface (FSS) rasorber based on four metallic FSS functional layers is proposed. The rasorber consists of two metallic FSS absorption layers, two metallic FSS transmission layers, and four corresponding dielectric isolation layers. The top absorption layer and third absorption layer are applied to generate a wide absorption band at high frequency and low frequency, respectively. The second and bottom transmission layers are adopted to generate a low-pass transmission band and bandpass transmission band, respectively. The multilayer structure of the rasorber guarantees the great span, broad bandwidth, and stable scattering characteristics. Moreover, we adopt the equivalent circuit model (ECM), surface current distribution, and loss distribution to comprehend the physical mechanism of the rasorber. The simulated results show that the transmission is -0.67 dB at 6.5 GHz, and the reflection below -10 dB ranges 1.5-4.6 and 9.2-13.7 GHz. To validate our design, we fabricated and measured the prototypes, and the measurement results show reasonable agreement with the simulated results.

Design of SOI MOSFETs for Analog/RF Circuits

In this paper, the concept of integration of a high voltage trench MOSFET (HVT MOSFET) and low voltage trench MOSFET (LVT MOSFET) is proposed. Insulator (Dielectric) isolation technique is used for the implementation of HVT and LVT MOSFETs on Silicon-on-Insulator (SOI) layer side by side. The HVT MOSFET consists of two gates which are placed in separate trenches in the drift region. The proposed structure minimizes ON-resistance (Ron) along with increased breakdown voltage (Vbr) due to reduced electric field, creation of dual channels, and folding of drift region in vertical direction. In HVT MOSFET, the drain current (ID) increases leading to enhanced trans conductance (gm) by simultaneous conduction of channels which improves the cut-off frequency (ft) and maximum oscillation frequency (fmax). On the other side, LVT MOSFET consists of a gate placed within a SiO2 trench to create two channels on either side of gate. The parallel conduction of two channels provides enhancement in ID, gm, fmax and ft. The performance analysis of HVT MOSFET and LVT MOSFET is carried out using 2D simulation in the device simulator (ATLAS).