Dielectric-breakdown-induced Epitaxy Research Articles

Impact of Gate Dielectric Breakdown Induced Microstructural Defects on Transistor Reliability

The impact of gate dielectric breakdown induced microstructural defects is investigated for both conventional poly-Si/SiON and metal-gate/high-k gate stacks. For poly-Si/SiON gate stacks, the effect of dielectric-breakdown induced epitaxy (DBIE) dilation on the post breakdown degradation rate is discussed. It was found that oxygen vacancy and Si-path formation in the breakdown path control the post-breakdown evolution from digital mode to analog mode which has significant impact on the post breakdown reliability margin. For metal-gate/high-k gate stacks, ultrafast degradation could happen with formation of metal filament if the compliance current level exceeds certain limit. However, the gate leakage current could recover from the breakdown damage by the reverse electrical biasing. The diffusion of oxygen atoms in and out of the breakdown path makes the ON/OFF switching of the percolation path possible.

Study of breakdown in ultrathin gate dielectrics using constant voltage stress and successive constant voltage stress

A comparative study on understanding the effect of conventional constant voltage stress (CVS) and successive constant voltage stress (SCVS) methodology on the post-breakdown transistor performance has been performed. In CVS stressing methodology, breakdowns in ultrathin gate oxides in narrow MOSFETs in moderate and high compliance current, Igl, range are usually associated with the formation of dielectric-breakdown-induced epitaxy (DBIE). Whereas in SCVS, due to a more controlled thermal environment in narrow MOSFET, DBIE is hardly found for breakdowns stressed under a similar Igl (as that of CVS in the moderate Igl) and gate oxide thickness. On the other hand, for both CVS and SCVS, once the DBIE is nucleated during progressive breakdown, its growth results in substantial gate dielectric thinning which is one of the mechanisms responsible for enhanced device degradation.

Dielectric-breakdown-induced epitaxy: a universal breakdown defect in ultrathin gate dielectrics

The breakdown phenomena in SiO/sub x/N/sub y/ (EOT=20 /spl Aring/) gate dielectric under a two- stage constant voltage stress in inversion mode are physically analyzed with the aid of transmission electron microscopy. The results show that dielectric-breakdown-induced epitaxy (DBIE) remains as one of the major failure defects responsible for gate dielectric breakdown evolution even for a stress voltage as low as 2.5 V. Based on the results, the same failure mechanism i.e., presence of DBIE would be responsible for the degradation in ultrathin gate dielectrics for gate voltage below 2.5 V. It is believed that DBIE will be present in MOSFETs failed at nominal operating voltage.

Breakdowns in high-k gate stacks of nano-scale CMOS devices

New failure mechanisms associated with breakdown in high-k gate stack consisting of HfO2/SiOx bilayered structure are presented. In addition to dielectric-breakdown-induced epitaxy (DBIE) commonly found in breakdowns in poly-Si/SiOxNy and poly-Si/Si3N4 MOSFETs, grain-boundary and field-assisted breakdowns near the poly-Si edge are found. A model based on breakdown induced thermo-chemical reactions has been developed to describe the physical microstructural damages triggered by breakdown in the high-k gate stack and the associated post-breakdown electrical performance. Some abnormal post-breakdown electrical behaviors such as recouping of the transistor’s saturated drain current, percolation resistance and transconductance are found to be common for high-k MOSFETs. Grain-boundary enhanced breakdown in annealed HfO2 films is of critical importance in degrading the reliability of high-k gate stacks.

Gate Dielectric-Breakdown-Induced Microstructural Damage in MOSFETs

Numerous failure mechanisms associated with hard breakdowns (HBD) in ultrathin gate oxides were physically studied with high-resolution transmission electron microscope (TEM). Migration of silicide from silicided gate and source/drain regions, abnormal growth of dielectric-breakdown-induced epitaxy (DBIE), poly-Si gate meltdown and recrystallization, severe damage in Si substrate, and total epitaxy of poly-Si gate and Si substrate of the entire transistor are among the common microstructural damages observed in metal-oxide-semiconductor field-effect transistors (MOSFETs) after HBDs in gate oxides (Gox) were observed electrically. The type of catastrophic failures and its degree of damage were found to be strongly dependent on the allowable current density and total resistance of the breakdown path during the breakdown transient. The physical analysis data from TEM analysis allow us to establish the sequence of the physical damage associated with the Gox HBD in narrow transistors. The proposed model is able to predict the next possible microstructural damage induced by HBD. Such knowledge will allow failure analysts to be able to retro-predict the current and power consumption in a field EOS/ESD failure based on the physical analysis and propose a knowledgeable guess on the potential root cause of the failures.

Percolation path and dielectric-breakdown-induced-epitaxy evolution during ultrathin gate dielectric breakdown transient

A physical model has been developed which complies with the experimental observation on the failure mechanism of ultrathin gate oxide breakdown during constant voltage stress. Dynamic equilibrium needs to be established between the percolation conductive path and the dielectric breakdown induced epitaxy (DBIE) formation during gate dielectric breakdown transient. The model is capable of linking the percolation model, soft breakdown, and hard breakdown to the DBIE growth for a variety of stress conditions and gate oxide thickness without involving new empirical parameters.

Correction to "Polarity-dependent dielectric breakdown-induced epitaxy (DBIE) in Si MOSFETs"

In the above-named work the Fig 1 caption was incorrect. The figure is presented with a corrected caption.

Polarity-dependent dielectric breakdown-induced epitaxy (DBIE) in Si MOSFETs

The physical evidence describing the structural deformation at the failure site of soft breakdowns (SBDs) in the 33-/spl Aring/ and 25-/spl Aring/ ultrathin gate oxide of narrow MOSFETs is reported. A "hillock" type epitaxial Si spot with size ranging from 2 to 100 nm associated with the gate-oxide breakdown failure is always found in the vicinity of the gate oxide and its formation depends strongly on the stress polarity. This epitaxial spot is believed to be induced by the breakdown event and this phenomenon can be named as polarity-dependent dielectric breakdown-induced epitaxy (DBIE).