Die Bond Process Research Articles

Study of Diebond Machine Platform on Theta Rotation Performance

Theta rotation on die during diebond process is one of the critical machine responses especially for land grid array (LGA) device with tight tolerances requirement. The paper focuses on the die theta rotation tolerance capability with critical design for LGA device evaluated on two different diebond machine platforms. The evaluation was narrowed down into two main diebond machines with the objective of attaining the best performance in terms of die theta rotation tolerance capability. The study used a side-by-side comparison analysis in terms of theta rotation on the two machines and presented the effect of machine selection on the theta rotation response. Theta rotation was monitored and both machines satisfied the specification of 1 degree of maximum rotation, though diebond Machine 1 was able to produce a more stable diebonding with only around less than 0.15 degree of theta rotation variation. For future works, the selected diebond machine could be used for devices with critical requirement.

Rubber-tip Design Improvement for Die Crack Elimination at Diebond Process

The paper focused on the elimination of die crack occurrence at the diebond process. Design of experiment (DOE) was done on the pick and place rubber-tip design and an improved design was finalized. The improved rubber-tip configuration with smaller vacuum design and full contact surface eventually resolved the die crack issues, improving the manufacturability of thin silicon die during diebond process. For future works, the configuration could be applied for packages with similar requirement.

Backside Metallization of Ag–Sn–Ag Multilayer Thin Films and Die Attach for Semiconductor Applications

Backside metallization, which offers the advantages of a thin die-attach layer, excellent ohmic contacts, good thermal dissipation, and electrical conduction, is a reliable die-attach method for high-temperature semiconductor devices. Optimized Ag–Sn–Ag thin film structures have been deposited as a backside metal layer and their mechanical and electrical characteristics evaluated as a replacement for conventional Au-based backside metal. The results confirmed that the Ag/Sn/Ag sandwich structure provided more reliable properties than the Sn/Ag and Ag/Sn structures. After the die-bonding process using the Ag/Sn/Ag backside metal, Cu6Sn5, Cu3Sn, and Ag3Sn intermetallic compounds were observed at the interface between the Si chip and Cu-plated Alloy 42 lead frame. The shear strength of the Ag/Sn/Ag backside metal was superior to that of conventional Au-12Ge backside metal, and its electrical characteristics met the requirement specifications of a commercial discrete semiconductor package.

Process Enhancement to Eliminate Adhesive Film Remains during Die Picking

Adhesive film remains on the dicing tape is one of the problems encountered in diebonding or die attach process during the pick-up process of silicon dies. With this occurrence, one method used to identify the root cause is the process mapping from wafer preparation to diebonding. Adhesive film remains are found occurring during the process, affecting the manufacturability and assembly yield of the semiconductor package. By resorting to a new and improved die attach adhesive film material, occurrence of its remains was mitigated during the diebonding process.

Warpage Mitigation through Diebond Process Improvement with Enhanced Leadframe Configuration

This paper presents an improvement in the design of quad flat no-leads (QFN) leadframe material to reduce the amount of unit rejection due to excessive leadframe warpage observed after die attach curing (DAC) process. The enhanced leadframe design includes modification through increasing the number of unit panels from 2 maps structure into 4-panel configuration to integrate mechanical relief for coefficient thermal expansion (CTE) mismatch between different material composition present inside the device. The implementation of this design in the assembly of QFN successfully reduced the amount of leadframe warpage into manufacturable level with positive impact in production output and assembly yield.

Characteristics Study of Die-Bond Process of High-Power LED Package

High-power light-emitting diodes (LEDs) are essential in general lighting applications. Because of the characteristics of semiconductors, the optical and electrical properties of LEDs vary with the operating temperature. To increase the reliability of high-power LEDs, this study conducted a shear stress test and examined the thermal dissipation alongside electrical and optical properties. The simulated and experimental trends of the thermal distribution of the LED package overlapped effectively. The results revealed that changing the side glue height from 10% to 100% of die height, which consequently increases the shear stress of 1693 g/mm2, reduces the thermal resistance of 1 °C/W, and reduces the luminous flux of 0.4 lm, can optimize the LED reliability.

Fabrication of Aluminum Nitride Thermal Substrate and Low-Temperature Die-Bonding Process for High Power LED

In this study, a low-cost aluminum nitride (AlN) sintering process to produce thick AlN film substrate with a high thermal conductivity is developed. The thermal conductivity of the present produced thick AlN film substrate is about 163.8 W/mK, which is very close to the reported thermal conductivity of the AlN material. Also, a Sn-Bi die-bonding system is developed to die-bond light emitting diodes (LEDs) on the present sintered AlN substrate with a relatively low die-bonding temperature (below 160°C). In this work, to enhance a better wetting at the die-bonding interface, three external forces (10 N, 15 N, and 20 N) were applied on LED chips during the die-bonding process. We found that the 15-N applied force can achieve a better die-bonding interface among three external forces (10 N, 15 N, and 20 N). The LED die-attached on the AlN substrates by 15 N normal force has the best shear strength (41.5 MPa), compared to the shear strength of 36.9 MPa and 31.5 MPa of the LED die-attached on AlN substrates by 20 N and 10 N normal force, respectively. The LED chips die-attached on the AlN substrate by 15-N normal force shows the best thermal resistance (7.3°C/W). The agreement between the thermal resistance tests and the shear strength tests implies that the better die-bonding interface produced a higher shear strength and a lower thermal resistance of the LED chips die-bonded on the AlN substrates.

Optimum Chip-Tape Adhesion for Reliable Pickup Process

An efficient UV-irradiation process plays an important role for a successful pickup of very thin ( $ ) Si chips, such as for integrated circuits, power semiconductors, or microelectromechanical systems devices. Before the UV-irradiation process, a dicing tape is laminated on the back of the wafer to hold it tightly (high adhesion strength), which enables rapid and smooth dicing of the wafer into separate Si chips. In the second stage, the adhesive layer is irradiated with UV light through the front side of the backing substrate, which decreases the adhesion strength to the level where the diced chips are picked up easily for further die-bonding processes. However, various malfunctions during the UV-irradiation process can lead to a different and occasionally insufficient UV dose. Consequently, the adhesion is not sufficiently reduced, which could later lead to pickup problems at the die-attach equipment during assembly. In this paper, we present the consequences of an insufficient UV dose on adhesion behavior and pickup efficiency. Using calculated adhesive energy, pickup simulation was done, and accumulated stress in the chips was evaluated at different UV doses. At lower UV doses, the adhesive energy showed rate-dependent behavior, while at higher UV doses, such a behavior was not shown. The accumulated stress within chips showed a linear correlation to adhesive energy, where at lower UV doses, the strength of the silicon chip was exceeded. In the practical process, with an increased pickup rate, higher energy is needed to delaminate the chip. With higher energy needed, accumulated stress in the chip is increased and could lead to the breaking of the chip.

Microstructural and thermal characterizations of light-emitting diode employing a low-temperature die-bonding material

A Sn/Bi bilayer was deposited on a hot air solder leveling (HASL)-treated metal-core printed circuit board (MCPCB) using electroplating as a low-temperature die-bonding material for light-emitting diode (LED). The eutectic feature of the Sn/Bi contact enabled the die-bonding process to accomplish through a liquid/solid reaction at 185°C with a proper compression force. A high-temperature die-bonding structure composed of a Bi layer sandwiched by two intermetallic compounds (IMCs) formed after thermocompression. Employment of the Sn/Bi bilayer for low-temperature die-bonding prevented the LEDs from thermal stress problems, and the resulting high-temperature IMC/Bi/IMC die-bonding structure was capable of withstanding multiple bonding reactions and high temperature/current operation environment. Durability tests including mechanical, thermal, and optical performance were systematically performed and compared with other commercially available die-bonding materials (Ag paste and solder alloys).

Laser Soldered Eutectic Die-Bonding Processes in LED Packaging

Laser Soldered Eutectic Die-Bonding Processes in LED Packaging

Laser Soldered Eutectic Die-Bonding Processes in LED Packaging

Laser Soldered Eutectic Die-Bonding Processes in LED Packaging

Analysis of Crack Formation in Germanium Substrate at AlInGaP Die Bonding Process

Cracked die is a serious failure mode in Light Emitting Diode (LED) industry – affecting the LED quality and long-term reliability performance. In this paper, an investigation has been carried out to find out a relation between die bonding force and the occurrence of die crack at Germanium (Ge) substrate due to die attach (DA) ejector pin indentation. Based on the analysis, the results show that cracks start to occur at 60 gram-force (gF) bond force and above. The crack length at the die substrate increases with respect to the bond force. These indented dies were further analyzed by using Scanning Electron Microscope (SEM). The results show plastic deformation, slip traces and material pile-up at the vicinity of ejector pin crater. Some samples were sectioned using Focus Ion Beam (FIB) and it was found the crack depth does not exceed beyond 20.5μm and it follows the (111) plane. These findings, concludes that cracks start to appear at 60gF and they are confined to surface level even indented at extreme load (140gF). These cracks are far away from the active region of LED.

Design of Self-Alignment Devices with Fluidic Self-Assembly for Flip Chip Packages in Batch Processing

An advanced LED multi-die-bonding integration using a fluidic self-assembly technique is proposed in the field of flip chip packages. Different form the conventional pick-and-place methods for a single LED die bonding, the fluidic approach is a relatively new design and a batch process, which can achieve not only die self-alignment but die self-assembly. Here, the size of LED die is 1-mm-square chip with the thickness of 0.3 mm. Due to the smaller size of LED die, the die-bonding process is still in need of finding a suitable approach and breakthrough. In this study, our design of fluidic self-assembly device is based on the experimental test and simulation results. The device design is the gas-flow channels with the magnetism. The width, height and length of each gas-flow channel are 1.1 mm, 0.5 mm, and 1 cm, respectively. With the restriction of the channel width, this structure design can control well to die self-alignment. In addition, the design of two circular structures in the channel can form a flat rim to achieve the die self-assemble. This mechanism of fluidic approach can be useful to the LED die self-alignment and self-assembly in the future batch processing.

Effect of Die-Bonding Process on MEMS Device Performance: System-Level Modeling and Experimental Verification

This paper presents a distributed nodal method (DNM) for compact modeling of the package-device interaction of microelectromechanical systems (MEMS). MEMS devices have movable structures that are sensitive to structural stresses and easily influenced by package structures and environmental parameters. Hence, it is necessary to include the packaged behavior of MEMS into a compact simulation tool with acceptable precision. The conventional nodal method is therefore modified to achieve this purpose. A node with distributed nodal quantities is defined to describe the distributed interactions among the device, package, and environmental temperature. Based on the definition, the related processes of element partition, nodal matrix formation, and element assembly have been demonstrated. The case of a die-bonded microbridge has been used as an example, since the microbridge is not only a typical MEMS structure but also is influenced easily by structural stresses. The DNM model is validated first by a finite-element method (FEM) simulation, then by two individual experiments, including the measurement of die warpage using a digital image correlation system and the detection of shifted natural frequencies of surface-micromachined bridges using a laser Doppler vibrometer system, both after die bonding. The FEM and test results agree with those evaluated by the model with a relative error of less than 10%. Stress alleviation of the test structure has been unintentionally achieved by die bonding, leading to relative shifts of 12%-26% and 19%-26% of the first and third natural frequencies of the microbridges. The packaged behavior also exhibits an evident distributed feature along the die surface as expected. Although, at current stage, the application of the DNM is still limited to static domain, it shows potential in developing hierarchical models of MEMS devices including the package.

イメージセンサチップ実装時の反り低減技術

We have developed a technique to reduce the chip warpage that results when a large sensor chip is bonded to a board. We performed a structure simulation that included the use of die-bond resins. We improved the die-bonding process, produced a prototype, and tested it. Results showed that it is possible to keep the warpage below 20μm even when a chip over 20 mm long is bonded to a printed circuit board with thermoset die-bond resins. We used our warp control technique to bend a sensor chip in the direction of the field curvature of a photographic lens. With the aim of deploying large sensors in the future, we performed a basic verification test of the tiling technique used to align multiple chips in a plane, developed a chip connection technique, and identified potential problems that could hamper the practical use of both.

Low Resistance Cathode Metallization and Die-Bonding in Silicon Carbide P-N Junction Diodes

We investigated how surface roughness, intentionally induced by chemical-mechanical polishing, affects the formation of ohmic contacts to an n-type 4H-SiC using a common circular transmission length method (CTLM). Nickel metal was used as the cathode ohmic contacts to n-type SiC. The specific contact resistance (SCR) for the un-polished sample (F1) and polished samples (F2 and F3) was 5.4 × 10-3 ⋅cm2 and 4.2 × 10-3 ⋅cm2, respectively. We found out that the un-polished sample (F1) had much higher SCR than the samples , F2 and F3. In addition, we did not see any difference between the differently polished samples, F2 and F3, indicating that there was no dependence on the face type of SiC (Si- or C-face) in the values of SCR. We also investigated the die-bonding processes with the surface roughness and metallization schemes' effects.

Sputtered full-wafer backside metallization for n-type InP: effect of temperature annealing

A full-wafer backside n-ohmic metallization scheme for InP is reported. The contact is formed by a single-step, all-sputter process and has been used successfully in three-inch InP opto-electronic device manufacturing. The metallization is based on the combination of a nickel–germanium–gold ohmic contact followed by a titanium–titanium nitride–titanium–gold metal stack. The titanium nitride layer acts as a barrier to grain boundary diffusion of indium and other material from the substrate to the surface of the top gold layer. The top gold is required for a gold–tin solder die bond process. The sputter process provides better than 5% cross-wafer and wafer-to-wafer thickness uniformity and a contact resistance of 2.5–8.3×10 −5 Ω cm 2. We report the fabrication process for this metal contact and the results of a full physical characterization by transmission electron microscopy, Auger survey and depth profile analysis and X-ray analysis.