Die-stacked Memory Research Articles

Application-Oriented Data Migration to Accelerate In-Memory Database on Hybrid Memory.

With the advantage of faster data access than traditional disks, in-memory database systems, such as Redis and Memcached, have been widely applied in data centers and embedded systems. The performance of in-memory database greatly depends on the access speed of memory. With the requirement of high bandwidth and low energy, die-stacked memory (e.g., High Bandwidth Memory (HBM)) has been developed to extend the channel number and width. However, the capacity of die-stacked memory is limited due to the interposer challenge. Thus, hybrid memory system with traditional Dynamic Random Access Memory (DRAM) and die-stacked memory emerges. Existing works have proposed to place and manage data on hybrid memory architecture in the view of hardware. This paper considers to manage in-memory database data in hybrid memory in the view of application. We first perform a preliminary study on the hotness distribution of client requests on Redis. From the results, we observe that most requests happen on a small portion of data objects in in-memory database. Then, we propose the Application-oriented Data Migration called ADM to accelerate in-memory database on hybrid memory. We design a hotness management method and two migration policies to migrate data into or out of HBM. We take Redis under comprehensive benchmarks as a case study for the proposed method. Through the experimental results, it is verified that our proposed method can effectively gain performance improvement and reduce energy consumption compared with existing Redis database.

Power Profiling of Modern Die-Stacked Memory

Die-stacked memories that integrate multiple DRAM dies into the processor package have reduced the interface bottleneck and improved efficiency, but demands for memory capacity and bandwidth remain unfulfilled. Additionally, the introduction of memory into the package further complicates heat removal. Memory power is therefore becoming a key architectural concern. To provide insight into these challenges, an architectural power model for High Bandwidth Memory is developed, validated, and used to provide detailed power profiles. Based on the resulting power trends, power is projected for potential future memory configurations with increased bandwidth and capacity. The results suggest that, without significant improvements in memory technology or architecture, the power utilization of in-package memories will continue to grow and limit the system power budget.

Reliability of 3D memories using Orthogonal Latin Square codes

Radiation is a cause of errors in electronics systems, especially on those deployed in space. Memories can suffer from different radiation effects including Single Event Upsets and Multiple Cell Upsets. These effects produce corruption of data and may cause a system malfunction. 3D die-stacked memories have been designed to increase bandwidth, reduce latency and limit power consumption. The shielding characteristic of the 3D structure causes a heterogeneous fault tolerance behaviour of the system where some of the inner dies are invulnerable while the outer dies require different protection levels. Orthogonal Latin Square codes are a class of error correcting codes that are modular and can provide different error correction degrees depending on the number of parity bits used. This paper proposed a solution based on current standards to provide dynamic and heterogeneous error correction capabilities to a 3D memory. To do so, Orthogonal Latin Square codes are used.

A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches

The resiliency problem of die-stacked memory will become important because of its lack of serviceability. This article details how to provide practical and cost-effective reliability, availability, and serviceability support for die-stacked DRAM cache architectures. The proposed approach can provide varying levels of protection, from fine-grained single-bit upsets to coarser-grained faults within the constraints of commodity non-error-correcting code DRAM stacks.