Abstract
Die-stacked memories that integrate multiple DRAM dies into the processor package have reduced the interface bottleneck and improved efficiency, but demands for memory capacity and bandwidth remain unfulfilled. Additionally, the introduction of memory into the package further complicates heat removal. Memory power is therefore becoming a key architectural concern. To provide insight into these challenges, an architectural power model for High Bandwidth Memory is developed, validated, and used to provide detailed power profiles. Based on the resulting power trends, power is projected for potential future memory configurations with increased bandwidth and capacity. The results suggest that, without significant improvements in memory technology or architecture, the power utilization of in-package memories will continue to grow and limit the system power budget.
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