Diameter Si Substrates Research Articles

Uniform broad-area deposition and patterning of SiO2 nanofilms by 172 nm photochemical conversion of liquid tetraethoxysilane layers at 300 K

Oxide films of the quality required for the fabrication of electronic and photonic devices are typically deposited at elevated temperatures and thermal equilibrium, thereby adversely impacting thermal budgets. We report the deposition and patterning of silicon dioxide (SiO2) films of high electrical and optical quality on Si(100) or polymer substrates in a N2 atmosphere and at 300 K by the photochemical conversion of thin liquid tetraethoxysilane (TEOS) layers with narrowband vacuum ultraviolet radiation [vacuum ultraviolet (VUV), 172 nm] provided by efficient microplasma lamps. Irradiating liquid TEOS layers, produced by spin-coating the precursor onto a substrate, with a VUV intensity of 13 mW cm−2, yields 40 nm-thick SiO2 films having a dielectric breakdown strength (Eb) of 5 MV cm−1, for which no precedent exists in the deposition of oxide films at 300 K. If room temperature-deposited films are post-annealed at 200 °C, Eb rises to 7.5 MV cm−1, which is <12% below the measured value (8.5 MV cm−1) for 40 nm SiO2 films grown by thermal oxidation. The deposition of 1 µm thick, stoichiometric SiO2 films requires only 20 min of VUV illumination at low optical fluences, and films with thicknesses of ∼35–60 nm exhibit a refractive index of 1.45 (633 nm). X-ray photoelectron spectrometry and Rutherford backscattering analysis indicate that, despite the deposition temperature, hydrocarbon impurity levels are near or below the detection limit. The capability for depositing 960 nm-thick SiO2 films uniformly (to within 0.6%) by liquid → solid photochemical conversion over a 5 cm diameter Si substrate and patterning films onto flexible polymer substrates has also been demonstrated.

(First Best Student Paper Award) Polymer to Silicon Direct Bonding for Microelectronics

Direct bonding consists in spontaneously bringing into contact two solid surfaces without any intermediate liquid. A liquid is defined here as a being thick enough to have fluid characteristics. Silicon direct bonding is widely used in microelectronics, for instance for the production of silicon-on-insulator substrates (for transistor manufacturing). Direct bonding can be performed between identical surfaces, for example, two silicon substrates. However, direct bonding is also feasible with two different surfaces such as silicon and metal.Direct bonding of two solid materials requires very strict surface conditions such as planarity, particle cleanliness and low surface roughness. The surface Root Mean Square (RMS) roughness should be lower than 0.5 nm for hydrophilic silicon bonding and 0.3 nm for hydrophobic silicon bonding [1].We will focus here on direct bonding with polymer films. It is a quite innovative bonding as polymers are materials with very different properties compared to silicon. They are indeed not crystalline, much less rigid and most of the time hydrophobic.Five different polymers thin films are used to evaluate direct bonding with polymers: LOR2A, BARC AR26N, SOC HM8102, TOK TDMR and LTC9310. Thicknesses are between 32 nm and 6 µm. Those polymers are deposited on 200 or 300 mm diameter Si substrates.First of all, polymers are characterized by Fourier-Transform Infrared Spectroscopy (FTIR), spectroscopic ellipsometry and Thermogravimetric Analysis (TGA). Contact angles of the different polymers are in the 58° to 77° range, a feature which is a characteristic of hydrophobic surfaces. For comparison, the contact angle is lower than 5° for hydrophilic silicon (SiO2) and 78° for hydrophobic H-passivated silicon (Si). The surface roughness of the five different polymers is evaluated by Atomic Force Microscopy (AFM), with RMS roughness ranging from 0.29 to 0.40 nm found. Such values are in-between the 0.3 nm and 0.5 nm thresholds for hydrophobic and hydrophilic surface bonding, respectively. However, direct bonding is feasible between polymers and hydrophilic or hydrophobic silicon surfaces in all cases. Bonding waves are observed and characterized by infrared imaging. Adhesion energies for bonding with the five different polymers are between 40 and 70 mJ/m². Meanwhile, the bonding wave velocity is in the 10-19 mm/s range. Data for polymer to hydrophilic silicon bonding are provided in Table 1. They can be compared to Table 2 data for hydrophilic and hydrophobic silicon bonding (i.e. ceramic bonding) as they have equivalent water contact angles. Polymer to Si direct bonding has higher adhesion energy and bonding wave velocity than SiO2 to Si ceramic direct bonding. The bonding interface, characterized by Scanning Acoustic Microscopy (SAM), does not reveal any bonding defects. Bonded stacks can be annealed at different temperatures. Acoustic images of bonding with BARC are shown in Figure 1 for different annealing temperatures. It is possible to measure their adherence energy after annealing using the DCB (Double Cantilever Beam) technique [2]. BARC adherence energies are given in Figure 2. As with ceramic bonding, bonding strengthens as the temperature increases. The covalent bonds density should increase during the annealing. The bonding degradation at 250°C and especially 300°C evidenced by Scanning Acoustic Microscopy (SAM) is in line with TGA findings on polymer degradation, with a threshold at 280°C. X-ray Photoelectron Spectroscopy is being used to identify interactions between the silicon surface and the polymer. A mechanism will be proposed for these innovative bondings.[1] H. Moriceau et al., « Overview of recent direct wafer bonding advances and applications », Adv. Nat. Sci. Nanosci. Nanotechnol., vol. 1, no 4, p. 043004, févr. 2011, doi: 10.1088/2043-6262/1/4/043004.[2] W. P. Maszara, G. Goetz, A. Caviglia, et J. B. McKitterick, « Bonding of silicon wafers for silicon‐on‐insulator », J. Appl. Phys., vol. 64, no 10, p. 4943-4950, nov. 1988, doi: 10.1063/1.342443. Figure 1

Distribution Evaluation of Optical Properties in Silicon Germanium Films Grown on Silicon Substrates with Graded Silicon Germanium Buffer Layers

Background and Objectives Silicon germanium (SiGe) is expected to be applied for the optical devices such as infrared sensors, because of its narrower band gap than Si. Therefore, it is important to understand the optical properties of SiGe. In general, SiGe films epitaxially grown on Si or Ge substrates are the candidate materials for the optical devices. Inhomogeneous dislocation and strain in the SiGe films may reduce process yields. Although there are some literatures regarding to the distribution of dislocations and strain in the SiGe films [1, 2], the optical properties have not been evaluated sufficiently yet. In this study, we investigate the distribution of optical properties in the SiGe films by spectroscopic ellipsometry. Experiments Graded SiGe buffer layers (10% Ge / μm) and strain-relaxed SiGe layers (6 μm) with Ge fraction of 20% and 50% were grown on 200 mm diameter Si (001) substrates by molecular beam epitaxy. It is widely recognized that the dislocation density and strain are reduced in the SiGe layer epitaxially grown on a graded buffer layer on a Si (001) substrate. Since the optical properties are affected by strain [3], this structure, which can reduce strain, is useful for applying SiGe films in optical devices. In order to investigate the distribution of the optical properties, strain and Ge fraction in the SiGe films, we measured several points from the center to the edge of the wafer by spectroscopic ellipsometry and X-ray diffraction (XRD). The spectroscopic ellipsometry measurements were performed with an incident angle of 70°, a 70 W xenon lamp as the light source, and a wavelength range of 200 to 1600 nm. For XRD, we measured the (004) plane using a Cu Kα X-ray source with a wavelength of 1.5406 Å. The lattice parameters were calculated based on the 004 diffraction peak from the SiGe films. Results and Discussion Figure 1 (a) and (b) show the distribution of the extinction coefficient in the SiGe films with Ge fraction of 20% and 50%, respectively. The distributions of the extinction coefficient in the infrared region are enlarged in these figures. We found that the extinction coefficient of SiGe (50%) is higher than that of SiGe (20%) in the near-infrared region, indicating that the higher Ge fraction is able to absorb longer wavelength light. From Fig. 1, it is clear that the SiGe wafer (50%) has a larger variation than the SiGe wafer (20%), especially in the long wavelength region.Figures 2 and 3 show XRD peak of SiGe films and the distribution of the lattice parameter in the SiGe films with Ge fraction of 20% and 50%, respectively. The lattice parameters of Si1-x Ge x assuming strain-free were calculated using Vegard's law (dx [Å] = 0.027x 2 + 0.2x + 5.431).From Fig. 3, it is clear that the SiGe wafer (50%) shows a larger variation than the SiGe wafer (20%) with respect to the lattice parameter. Since the lattice parameter of SiGe varies with the Ge fraction and strain state, first the cause of this variation can be cited that of the Ge fraction. The lattice parameters at the edge of the wafers are much larger than those at the center of the wafers, suggesting that variations in Ge fraction at the edge of the wafers. The same behavior has been observed in previous studies regarding SiGe wafers [1, 2]. Also, it is considered that the variations of the lattice parameter vary not only due to Ge fraction, but also residual strain. Although sample structures are designed to induce strain relaxation in SiGe films, it is considered that the strain in the epitaxially grown SiGe film on the graded buffer layer cannot be fully relaxed based on the results of XRD. These variations of Ge fraction and strain may cause the variation of the extinction coefficient of SiGe films.The result that the SiGe wafer (50%) has a larger variation than the SiGe wafer (20%) indicates that the inhomogeneity of the optical properties and the lattice parameter increase and it may reduce process yields with increasing Ge fraction, for SiGe films on Si substrates.

Photodiodes based on p-on-n junctions formed in MBE-grown n-type MCT absorber layers for the spectral region 8 to 11 μm

Results of measurement of the dark currents and photocurrents of p-on-n photodiodes (PD) formed in In-doped MBE-grown n-type mercury cadmium telluride (MCT) films are reported. We used 3 in. in diameter (0 1 3) GaAs and (0 1 3) Si substrates. The p-on-n junctions were fabricated using the implantation of As+ ions followed by the thermal annealing activation. It was shown that the regime of background-limited performance (BLIP) of the p-on-n PD with experimentally measured long-wave cutoff wavelength (LW) cutoff (λc) of 11.1 and 10.3 μm at 77 K is observed up to elevated temperatures of 105 K and 117 K, respectively. The temperature dependence of the noise equivalent temperature difference (NETD) for p-on-n PD sized 30 × 30 μm was calculated taking into account only PD shot noise. It was shown that such LW p-on-n photodiodes allows to increase the operating temperature of IR FPA detectors up to 100–105 K with the NETD less than 30 mK.

Epi-Gd2O3/AlGaN/GaN MOS HEMT on 150 mm Si wafer: A fully epitaxial system for high power application

In this letter, we report the impact of epitaxial Gd2O3 on the electrical properties of an AlGaN/GaN high electron mobility transistor (HEMT) grown on a 150 mm diameter Si (111) substrate. Incorporation of epitaxial Gd2O3 grown by the molecular beam epitaxy technique under a metal gate (metal/Gd2O3/AlGaN/GaN) causes six orders of magnitude reduction in gate leakage current compared to metal/AlGaN/GaN HEMT. We observe that epi-Gd2O3 undergoes complete structural changes from hexagonal to monoclinic as the thickness of the layer is increased from 2.8 nm to 15 nm. Such structural transformation is found to have a strong impact on electrical properties whereby the gate leakage current reaches its minimum value when the oxide thickness is 2.8 nm. We find a similar trend in the density of interface traps (Dit) having a minimum value of 2.98 × 1012 cm−2 eV−1 for the epioxide layer of thickness 2.8 nm. Our measurements also confirm a significant increase in the two dimensional electron gas (2DEG) density (∼40%) at AlGaN/GaN interface with epioxide grown on AlGaN, thus confirming the contribution of epitaxial lattice strain on 2DEG modulation.

Low Power Thermal Tuning in Resonant Vertical Junction Silicon Modulators Through Substrate Removal

We report on thermally tunable modulators, with efficiencies up to 2.16 nm/mW. Efficient performance was accomplished through integrated heater design and Si substrate removal, where the heavily N+ doped Si heater element is integrated into the body of the microdisk. For comparison, modulators with an external heater design were also tested with small diameter Si substrate removed. The external heavily doped N+Si heater bars were fabricated outside the diameter of the microdisk. Efficiency for external heater design was 0.68 nm/mW with substrate removed. Both types of thermal modulators were experimentally tested and simulated for a complete understanding of the Si substrate's influence on heat dissipation with both types benefiting significantly from substrate removal. Agreement between simulation and experimental results was greater than 80 $\%$ in all instances.

Direct-Write Laser Greyscale Lithography for Multi-Layer Lead Zirconate Titanate Thin Films.

Direct-write laser greyscale lithography has been used to facilitate a single step patterning technique for multi-layer lead zirconate titanate (PZT) thin films. A 2.55 μm thick photoresist was patterned with a direct-write laser. The intensity of the laser was varied to create both tiered and sloped structures that are subsequently transferred into multi-layer PZT(52/48) stacks using a single Ar ion mill etch. Traditional processing requires a separate photolithography step and an ion mill etch for each layer of the substrate, which can be costly and time consuming. The novel process allows access to buried electrode layers in the multi-layer stack in a single photolithography step. The greyscale process was demonstrated on three 150 mm diameter Si substrates configured with a 0.5 μm thick SiO2 elastic layer, a base electrode of Pt/TiO2, and a stack of four PZT(52/48) thin films of either 0.25 μm thickness per layer or 0.50 μm thickness per layer, and using either Pt or IrO2 electrodes above and below each layer. Stacked capacitor structures were patterned and results will be reported on the ferroelectric and electromechanical properties using various wiring configurations and compared to comparable single layer PZT configurations.

Atomistic Approach for Modeling the Wafer Curvature for Pseudo-Morphic and Non-Pseudo-Morphic Epitaxial Multilayer Structures

During last few decades, there have been tremendous progress in the development of III-V based and III-Nitride based devices, namely High Electron Mobility Transistors (HEMT) and Light Emitting Diodes (LEDs). Research interest has recently shifted towards III-V compound semiconductor epitaxy on large diameter (200 mm) Si substrates in order to realize III-V-on-Si and CMOS integration. Due to large lattice and thermal mismatch between III-V and Si materials, e g. GaN-on-Si wafers experience large internal stresses and significant wafer bow. The wafer bow is severe for large wafers (for a given radius of curvature, the wafer bow increases by 125% for 150 mm and 300% for 200 mm diameter wafers compared to 100 mm wafers). This results in wafer fragility issues, as well as difficulties in subsequent handling and processing of such wafers. These issues are typically addressed using thicker Si substrates and careful design of buffer layers. While there are many experimental efforts to overcome these challenges, there are only limited reports that try to properly explain and understand the mechanism of wafer curvature. An appropriate theoretical model which predicts the final wafer curvature for given epilayer designs would greatly improve our ability to design optimal buffer and device layers. There are so far two main models for epitaxial multilayers which relate the wafer curvature to the strain state and the material properties of each layer. Ohlsen et al. (J. App. Phys. 1977) derived an analytical expression for the stress in each layer and the final wafer curvature for a given layer stack. This model however does require one to define strain states in each layer which is not straightforward to predict prior to the actual hetero-epitaxy of complex layers with large misfit dislocation densities such as in the GaN-on-Si system. Usher et al. (Phys. Rev. B 2003) proposed an atomistic approach for analyzing pseudo-morphic multi-layer structures, and were able to provide a closed form equation for radius of curvature. However, none of the reports have explicitly considered the thermal strain in the calculation. In this presentation we would address these limitations and provide a complete description of the wafer curvature including the effects of both lattice mismatch and coefficient of thermal expansion mismatch. We extend the atomistic approach to calculate the radius of curvature for non-pseudomorphic systems like III/V-on-Si systems. The density of misfit dislocations at each interface is used as a parameter to define the effective lattice constant of partially relaxed epilayers at the interface. Subsequently the lattice constant at any point in each layer is defined with respect to the interface lattice constant and is used to calculate the strain. Then the total strain energy of the resulting system is calculated as a function of system curvature, with the minimum energy solution corresponding to the predicted final curvature of the wafer. For better accuracy each epitaxial layer may be divided to separate sublayers with individual misfit dislocation density values. For illustration GaN-3xAlGaN-AlN-Si system was considered and radius of curvature was predicted. The accuracy of the model depends on the accuracy with which the misfit dislocation density is known. Experimental techniques like TEM and electron beam induced current (EBIC) can be used to estimate or quantify the number of dislocated atoms. Finally, we will include the thermal effect within the atomistic approach to be able to predict in-situ curvature of III/V-on-Si systems which will be helpful in designing the growth experiments for various devices.

Investigation of AlGaN/GaN high electron mobility transistor structures on 200-mm silicon (111) substrates employing different buffer layer configurations.

AlGaN/GaN high electron mobility transistor (HEMT) structures are grown on 200-mm diameter Si(111) substrates by using three different buffer layer configurations: (a) Thick-GaN/3 × {AlxGa1−xN}/AlN, (b) Thin-GaN/3 × {AlxGa1−xN}/AlN, and (c) Thin-GaN/AlN, so as to have crack-free and low-bow (<50 μm) wafer. Scanning electron microscopy, energy-dispersive X-ray spectroscopy, high resolution-cross section transmission electron microscopy, optical microscopy, atomic-force microscopy, cathodoluminescence, Raman spectroscopy, X-ray diffraction (ω/2θ scan and symmetric/asymmetric ω scan (rocking curve scan), reciprocal space mapping) and Hall effect measurements are employed to study the structural, optical, and electrical properties of these AlGaN/GaN HEMT structures. The effects of buffer layer stacks (i.e. thickness and content) on defectivity, stress, and two-dimensional electron gas (2DEG) mobility and 2DEG concentration are reported. It is shown that 2DEG characteristics are heavily affected by the employed buffer layers between AlGaN/GaN HEMT structures and Si(111) substrates. Particularly, we report that in-plane stress in the GaN layer affects the 2DEG mobility and 2DEG carrier concentration significantly. Buffer layer engineering is shown to be essential for achieving high 2DEG mobility (>1800 cm2/V∙s) and 2DEG carrier concentration (>1.0 × 1013 cm−2) on Si(111) substrates.

Comparison of electrical, optical and structural properties of epitaxially grown HEMT's type AlGaN/AlN/GaN heterostructures on Al2O3, Si and SiC substrates

In this work we present the results of experimental studies on HEMT's (High Electron Mobility Transistor) type AlGaN/GaN heterostructures deposited by MOVPE (Metal Organic Vapor Phase Epitaxy) on two inch diameter Al2O3, Si and SiC substrates. The layer structure as well as detailed grown conditions of buffer layers of the investigated structures are described. The main attention is paid to comparison of the properties of nominally the same, AlGaN/GaN heterostructures deposited on the different substrates. SEM investigations show significant differences in size of hexagonal shaped mosaic observed on the surface of AlGaN/AlN/GaN heterostructures. In this paper an effort is made to explain the mechanism of grooves and micro-pits formation in the heterostructures deposited on Al2O3, Si and SiC substrates. The AlGaN/AlN/GaN heterostructures electrical parameters, investigated by impedance spectroscopy, optical properties measured by room temperature photoluminescence and surface morphology examined by scanning electron microscopy are presented and discussed. In addition, XRD measurments results are presented. All samples, regardless of the used substrate, exhibit good electrical performance with sheet carrier concentration and mobility of 2DEG (Two Dimensional Electron Gas) above 0.95 × 1013 cm−2 and 1450 cm2 V−1 s−1, respectively. Depending on the substrate type, distinct positions of AlGaN and GaN related photoluminescence peaks are observed. It is shown, that structures grown at the same conditions on different substrates, exhibit different electrical and optical behavior as a result of the different material quality and a surface microstructure.

Gold-free contacts on AlxGa1-xN/GaN high electron mobility transistor structure grown on a 200-mm diameter Si(111) substrate

The authors report on the fabrication and characterization of low-temperature processed gold-free Ohmic contacts for AlxGa1−xN/GaN high electron mobility transistors (HEMTs). The HEMT structure grown on a 200-mm diameter Si(111) substrate is used in this study. Using the Ti/Al/NiV metal stack scheme, the source/drain Ohmic contact optimization is accomplished through the variation of Ti/Al thickness ratio and thermal annealing conditions. For an optimized Ti/Al stack thickness (20/200 nm) annealed at 500 °C for 30 s with smooth contact surface morphology, a specific contact resistivity of ∼6.3 × 10−6 Ω cm2 is achieved. Furthermore, with gold-free Ni/Al gates, the fabricated HEMTs exhibit ION/IOFF ratio of ∼109 and a subthreshold swing of ∼71 mV/dec. The demonstrated gold-free contact schemes thus provide a solution toward the implementation of GaN-based HEMT process on a Si foundry platform.

Structural properties of In0.53Ga0.47As epitaxial films grown on Si (111) substrates by molecular beam epitaxy

In0.53Ga0.47As epitaxial films are grown on 2-inch diameter Si (111) substrates by growing a low-temperature In0.4Ga0.6As buffer layer using molecular beam epitaxy. The effect of the buffer layer thickness on the as-grown In0.53Ga0.47As films is characterized by X-ray diffraction, scanning electron microscopy, atomic force microscopy and transmission electron microscopy (TEM). It is revealed that the crystalline quality and surface morphology of as-grown In0.53Ga0.47As epilayer are strongly affected by the thickness of the In0.4Ga0.6As buffer layer. From TEM investigation, we understand that the type and the distribution of dislocations of the buffer layer and the as-grown In0.53Ga0.47As film are different. We have demonstrated that the In0.4Ga0.6As buffer layer with a thickness of 12nm can advantageously release the lattice mismatch stress between the In0.53Ga0.47As and Si substrate, ultimately leading to a high-quality In0.53Ga0.47As epitaxial film with low surface roughness.

High Brightness, Large Scale GaN Based Light-Emitting Diode Grown on 8-Inch Si Substrate

A crack-free, uniform InGaN/GaN light-emitting diode (LED) structure with strain-engineered buffer layer was grown on an 8-inch diameter Si(111) substrate. The full width at half maximum (FWHM) of (002) and (102) ω-scan is 280 and 420 arcsec, respectively. For LED on 8-inch Si, multiple quantum well (MQW) photoluminescence (PL) wavelength uniformity of 0.55% (2.4 nm) has been achieved by using proper curvature engineered wafer carrier. We demonstrated high brightness 1×1 mm2 LED devices utilizing vertical chip process then evaluated their device properties. The electro-optical characteristics of the fabricated vertical LED (VLED) shows around 1 W light output power at 1 A injection current with operating voltage of 4.0 V.

Probing channel temperature profiles in AlxGa1−xN/GaN high electron mobility transistors on 200 mm diameter Si(111) by optical spectroscopy

Using micro-Raman and photoluminescence (PL) techniques, the channel temperature profile is probed in AlxGa1-xN/GaN high electron mobility transistors (HEMTs) fabricated on a 200 mm diameter Si(111) substrate. In particular, RuOx-based gate is used due to the semitransparent nature to the optical excitation wavelengths, thus allowing much accurate thermal investigations underneath the gate. To determine the channel temperature profile in devices subjected to different electrical bias voltages, the GaN band-edge PL peak shift calibration with respect to temperature is used. PL analyses show a maximum channel temperature up to 435 K underneath the gate edge between gate and drain, where the estimated thermal resistance in such a HEMT structure is about 13.7 KmmW−1 at a power dissipation of ∼10 W/mm. The temperature profiles from micro-Raman measurements are also addressed from the E2-high optical phonon peak shift of GaN, and this method also probes the temperature-induced peak shifts of optical phonon from Si thus showing the nature of thermal characteristics at the AlN/Si substrate interface.

Effects of lift-off and strain relaxation on optical properties of InGaN/GaN blue LED grown on 150 mm diameter Si (111) substrate

We report on the effect of strain relaxations induced by lift-off in an InGaN/GaN multiple quantum wells (MQWs) blue light-emitting diode (LED) structure grown by metal-organic chemical vapor deposition (MOCVD) on a 150-mm diameter Si (111) substrate. To manage the lattice strain and, meanwhile, filter the threading dislocations, an AlN nucleation layer followed by a fourfold-step-graded AlGaN buffer together with multiple low-temperature AlN interlayers hasbeen employed, which results in a crack-free growth of 4.9-µm GaN on Si (111) in the studied LED structure. High-resolution x-ray diffraction (HRXRD) and micro-Raman spectroscopy reveal that MQWs are coherently grown on the GaN layer while the GaN layer is tensile strained on the Si (111) substrate. Lift-off by wet-chemical etching results in phonon softening of both the top-layer GaN and the InGaN within the QWs; meanwhile, a red-shift of ~11meV in the photoluminescence (PL) from the MQWs accompanied by a significant decrease (>4.9 times) in the PL-peak decay time is observed at room temperature. These observations are discussed and associated with the lift-off induced strain relaxations, which change the wafer curvature that in turn results in redistribution of in-plane stresses along the growth direction in the GaN-on-Si LED structure.

(Invited) High Brightness, Large Scale GaN Based Light-Emitting Diode Grown on 8-Inch Si Substrate

GaN based light-emitting diodes(LEDs) grown on a Si substrate is one of promising future technologies in LED industry due to its scalability and costeffectiveness compare to the conventional sapphire based LEDs.One of major technical issues in GaN/Si LED is the severemismatch oflattice and thermal expansion coefficientsbetween GaNand Si, which induces significant tensile strain in the GaNepilayer that often leads to wafer cracking. Optical loss by the absorbing Si substrate is another barrier to overcome for realizing high-brightness LEDs competitive to those on sapphire or SiC substrates.In this study, we demonstrated blue LEDs grown on 8-inch diameter Si substrate and fabricated high brightness devicesutilizing vertical chip process Thecrack-free InGaN/GaN LED waferswith strain-engineered buffer structure were grown on 8-inch diameter Si(111) substrates by metalorganic chemical vapor deposition (MOCVD) system (Veeco TurboDisk k465i).The optimized growth conditions of AlN buffer layer improved the crystalline quality of GaNepilayers. The FWHM of (002) and (102) ω-scan is 280 and 420 arcsec, respectively. These values are comparable to the best reported so far for GaN on silicon. The surface morphology of GaN layer investigated using atomic force microscopy (AFM) exhibits very smooth surface and clear atomic step flow patterns. The root-mean-square (RMS) roughness is 0.15 nm in a 5x5 μm2 scan area.For LED on 8-inch Si, MQW PL wavelength uniformity of ~0.5% (2.4 nm) has been achieved using the proper strain/curvature engineering with optimized wafer carrier designs. These are among the lowest values reported to date.After the epitaxial growth with silicon substrate, a 1mm × 1mm sized vertical type LED(VLED) was fabricated using both wafer bonding process and Si removing process. While the GaN on sapphire employs a laser lift-off technique to remove the substrate, we developed the wet etching process in order to remove the silicon substrate without any damageon the surface of LED structure. The electro-optical characteristics of the fabricated VLED in this work shows good efficiency(almost 1W light power at 1A inject current) with operating voltage of 4.0V.

(Invited) High Brightness, Large Scale GaN Based Light-Emitting Diode Grown on 8-Inch Si Substrate

A crack-free, uniform InGaN/GaN light-emitting diode (LED) structure with strain-engineered buffer layer was grown on an 8-inch diameter Si(111) substrate. The full width at half maximum (FWHM) of (002) and (102) ω-scan is 280 and 420 arcsec, respectively. For LED on 8-inch Si, multiple quantum well (MQW) photoluminescence (PL) wavelength uniformity of 0.55% (2.4 nm) has been achieved by using proper curvature engineered wafer carrier. We demonstrated high brightness 1 x 1 mm2 LED devices utilizing vertical chip process then evaluated their device properties. The electro-optical characteristics of the fabricated vertical LED (VLED) shows around 1 W light output power at 1 A injection current with operating voltage of 4.0 V.

Structural and optical properties of AlxGa1−xN/GaN high electron mobility transistor structures grown on 200 mm diameter Si(111) substrates

The authors report on the study of homogeneity in structural and optical properties of AlxGa1−xN/GaN high electron mobility transistor (HEMT) structures grown on 200 mm diameter Si(111) substrates. The consequence of a variation of buffer layer thicknesses as well as the interface quality has been studied by in-situ growth monitoring. A reasonably good uniformity of crystalline quality in the heterostructures grown with a lower wafer bowing has been observed from the full width at half maxima of symmetric as well as asymmetric high resolution x-ray diffraction scans across the wafer. Furthermore, the thickness and Al content of the AlxGa1−xN barrier layer across the wafer is found to be uniform when the wafer bowing is lower. Optical and electrical measurements across the epiwafer address the strain homogeneity, luminescence, and two-dimensional electron gas properties. Based on these studies of growth optimization, HEMT epiwafers with a total nitride stack thickness of 4.4 μm with a wafer bowing &amp;lt;50 μm on 1.0 mm thick Si substrates are demonstrated.

InxAl1-xN/AlN/GaN High Electron Mobility Transistor Structures on 200 mm Diameter Si(111) Substrates with Au-Free Device Processing

InxAl1-xN/AlN/GaN-based high electron mobility transistor (HEMT) structures are epitaxially grown on 200 mm diameter Si(111) substrates by a metal organic chemical vapor deposition technique. The structural and electrical properties of the nitride layers are addressed by high-resolution X-ray diffraction and Hall effect measurements. The fabricated HEMTs with Au-free contact metallization schemes have resulted in an ON-OFF current ratio ∼105. Ti/Al/Ni/W-based Ohmic source/drain contacts, with 1.5 μm RuOx Schottky gate on In0.15Al0.85N/AlN/GaN HEMTs at VDS = 10 V, show a maximum transconductance (gm) and saturation drain current (IDSAT) of 0.19 ± 0.01 S/mm and 0.82 ± 0.02 A/mm, respectively, with a reasonable uniformity from the center to edge of a 200 mm diameter epiwafer.

Synthesis of large area carbon nanosheets for energy storage applications

We report the large area growth of highly conductive carbon nanosheets (CNS) composed of few layer graphene on 200mm diameter Si substrates using conventional radio frequency plasma-enhanced chemical vapour deposition. Raman spectroscopy is used to characterise the evolution of the CNS nucleation and growth with time in conjunction with TEM revealing the nano-sized graphene-like nature of these films and the intimate contact to the substrate. An individual sheet can have edges as thin as 3 graphene layers. The influence of the growth support layer is also discussed as film growth is compared on titanium nitride (TiN) and directly on Si. Electrochemical cyclic voltammogram (CV) measurements reveal these layers to form an excellent electrical contact to the underlying substrate with excellent stability towards oxidation whilst having a large electrochemical surface area. The resistance of a 150nm film was measured to be as low as 20μohmcm. The high percentage of narrow few layer graphene edge sites exposed allows for faster electrochemical reaction rates compared to carbon nanotubes (CNTs) and other electrode materials (glassy carbon and Pt).