DFE Receiver Research Articles

A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology

A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology

Reduced Complexity Detection in MIMO Systems with SC-FDE Modulations and Iterative DFE Receivers

This paper considers a Multiple-Input Multiple-Output (MIMO) system with P transmitting and R receiving antennas and different overall noise characteristics on the different receiver antennas (e.g., due to nonlinear effects at the receiver side). Each communication link employs a Single-Carrier with Frequency-Domain Equalization (SC-FDE) modulation scheme, and the receiver is based on robust iterative frequency-domain multi-user detectors based on the Iterative Block Decision Feedback Equalization (IB-DFE) concept. We present low complexity efficient receivers that can employ low resolution Analog-to-Digital Converters (ADCs) and require the inversion of matrices with reduced dimension when the number of receive antennas is larger than the number of independent data streams. The advantages of the proposed techniques are particularly high for highly unbalanced MIMO systems, such as in the uplink of Base Station (BS) cooperation systems that aim for Single-Frequency Network (SFN) operation or massive MIMO systems with much more antennas at the receiver side.

A 5-bit 1.8 GS/s ADC-based receiver with two-tap low-overhead embedded DFE in 130-nm CMOS

Along with CMOS technology scaling, ADC-based serial link receivers have drawn growing interest in backplane communications but power dissipation of the ADC and complex digital equalizer in such digital receivers can be a limiting factor in high-speed applications. Implementing analog embedded equalization within the front-end ADC structure can potentially relax the ADC resolution requirement and reduces the complexity of the DSP which results in a more energy-efficient receiver. In this paper, the equivalence between the speculative comparisons of a loop-unrolling DFE and an ADC with non-uniform quantization levels is utilized to propose a novel ADC-based DFE receiver structure. The equivalency partially compensates for the power overhead imposed by loop-unrolling DFE. The 5-bit prototype receiver with two-tap embedded DFE is designed, laid out and simulated in a 130-nm CMOS process with 1.8 Gbps data rate. With embedded DFE disabled, the receiver achieves 4.57-bits ENOB and 1.77 pJ/conv.-step FOM. With 1.8-Gbps signaling across a 48-in FR4 channel, the two-tap DFE enabled receiver opens the completely closed eye and allows for a 0.26 UI timing margin at a BER of 10−9. The total active area is 0.21 mm2 and the ADC consumes 76 mW from a 1.2-V supply.

Current-Integrating DFE with Sub-UI ISI Cancellation for Multi-Drop Channels

This paper presents a half-rate currentintegrating DFE receiver with sub-unit interval (sub-UI) inter-symbol interference (ISI) cancellation. By having a single additional DFE tap in each data path, the proposed DFE receiver can minimize BER degradation due to input pattern dependency and feedback tap latency problems in conventional current-integrating DFE receivers. The proposed DFE receiver was designed and fabricated in a 45 nm CMOS process, whose measurement results indicated that the BER bathtub width is increased from 0.235 UI to 0.315 UI (34% improvement) at 10 -12 BER level.

A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth

A 16 Gb/s I/O link receiver fabricated in 22 nm CMOS SOI technology is presented. Attenuation and ISI of transmitted NRZ data across PCB channels are equalized with a CTLE feeding an 8-tap DFE. The first tap uses digital speculation and the following seven taps are realized by means of the switched-capacitor technique. Timing recovery and control are performed with a Mueller-Müller type-A baud-rate CDR. The architecture is half-rate and requires one phase rotator. In total, each slice has six comparators to recover data and timing information. The secondorder digital CDR operates at quarter-rate and features a low-latency implementation of the proportional path. At 16 Gb/s, 1 Vppd PRBS31 data transmitted without FFE equalization is recovered across a PCB channel with 34 dB attenuation at 8 GHz. The measured tracking bandwidth is 31 kppm (16 GHz ± 496 MHz), and an amplitude of 3 UIPP is tolerated at 1 MHz sinusoidal jitter. The sinusoidal jitter amplitude tolerance measured at 10 Gb/s is 0.4 UIPP at 10 MHz and remains above 0.2 UIPP up to 1 GHz with PRBS31 data recovered (BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> ) across a PCB channel with 27 dB attenuation at 5 GHz. The power efficiency is 3.7 mW/Gb/s, including the full-rate clock receiver.

Symbol-Rate Clock Recovery for Integrating DFE Receivers

Symbol-Rate Clock Recovery for Integrating DFE Receivers

A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface

A 3.8 Gb/s multi-drop single-ended integrating DFE (IDFE) receiver is implemented in a 0.18 um CMOS by using a single-loop LMS-algorithm to find the DFE coefficients automatically. Initially, a preamble input data pattern ('1101') is applied to the main IDFE circuit to determine the DFE coefficients, while a fixed input data pattern ('1111') is applied to the replica IDFE circuit. The difference between the outputs of the two IDFE circuits is used in the feedback loop to determine the DFE coefficients. The reference voltage (Vref) of preamplifier is generated inside chip by a Vref loop to reduce the effect of the external noise and the input offset voltage of preamplifier and IDFE circuits and also to track the mid-level of the input data swing in spite of process variations of TX chips. An integrating deskew scheme with a minimum overhead is introduced. 2-drop and 4-drop DRAM channels are tested. The maximum data rate was increased from 1.0 Gb/s to 2.6 Gb/s by DFE in the heavily loaded 4-drop interface, from 3.5 Gb/s to 3.8 Gb/s by DFE in the 2-drop interface.

A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication

This paper presents a 1.5 to 10 Gb/s SATA/SAS/FC receiver in 65 nm CMOS. The multiple constraints set by industry standards ask for a receiver architecture capable of simultaneously addressing channel loss impairments, high frequency-difference tracking and low serial to parallel latency. An adaptive 3-tap DFE data recovery is based on a direct-feedback topology to provide a continuous equalized signal assuring a robust clock-data self alignment. A latch-based DFE topology has been developed to overcome the classical DFE feedback loop-delay issue. A digital early-late clock recovery has been proven for plusmn5000 ppm SSC tracking. Extensive digital features allow self-calibration and internal eye analysis. The device, realized in a 65 nm technology, supports more than 36" FR4 at 6 Gb/s with SSC and 28" at 8.5 Gb/s while keeping 0.4 UI of additional sinusoidal jitter tolerance, consuming 140 mW from 1V.

Highly Efficient Sparse Multipath Channel Estimator with Chu-Sequence Preamble for Frequency-Domain MIMO DFE Receiver

In this paper, a sparse multipath channel estimation algorithm is proposed for multiple-input multiple-output (MIMO) single-carrier systems with frequency-domain decision feedback equalizer (FD-DFE). This algorithm exploits the orthogonality of an optimal MIMO preamble based on repeated, phase-rotated, Chu (RPC) sequences, leading to a dramatic reduction in computation. Furthermore, the proposed algorithm employs an improved non-iterative procedure utilizing the Generalized AIC criterion (GAIC), resulting in further computational saving and performance improvement. The proposed scheme is simulated for 802.16d SCaPHY and SUI-5 sparse channel model under a 2 x 2 spatial multiplexing scenario, with the MIMO FD-DFE as the receiver. The result shows that the channel estimation accuracy is significantly improved, and the performance loss compared to the known channel case is only 0.7 dB at the BER of 10 -3 .

An Efficient DFE &amp; ML Suboptimum Receiver for Data Transmission Over Dispersive Channels Using Two-Dimensional Signal Constellations

The DFE & ML receiver is presented for data transmission systems using QAM modulation. A substantial improvement in performance results as compared to other one- or two-stage receiver structures at relatively low computational complexity.

Adaptive Equalization of Channel Nonlinearities in QAM Data Transmission Systems

Within the population of voiceband telephone channels, few channel characteristics are as pervasive in their impairment of high-speed data communication as nonlinear distortion, which cannot be removed or equalized in the receiver as easily as can linear distortion. The purpose of this paper is to report on an investigation of a QAM receiver incorporating adaptive equalization of nonlinearities as well as adaptive decision feedback equalization and data-aided carrier recovery for mitigation of linear distortion and phase jitter, respectively. Nonlinearities are equalized by adding to the received in-phase and quadrature signals a weighted sum of nonlinear functionals of the received signal and of modulated previous receiver decisions. The choice of nonlinear terms in the sum is based on a channel model incorporating quadratic and cubic nonlinearities as well as linear dispersive elements. The adjustment of the weighting, or tap, coefficients for the various terms is based on a gradient algorithm, as is the adjustment of the linear tap coefficients and the carrier phase reference. The feasibility of nonlinearity equalization on real voiceband channels was confirmed in a test in which recorded 9600-bps QAM signals, received from a worse-than-average set of 17 voiceband telephone channels, were processed by a computer-simulated version of the proposed receiver (termed the NL receiver). The observed error rates for all channels were lower, in some cases by several orders of magnitude, than those achieved by computer-simulated versions of the linear receiver and of a decision feedback equalization receiver (termed the DFE receiver).