Device Self-heating Effect Research Articles

Analysis of thermal stability in underlap and overlap DMG FinFETs including self-heating effects

This work investigates the impact of the self-heating effect (SHE) on SOI Dual-Material Gate (DMG) FinFETs with channel engineering including gate underlapped and overlapped structures. Both these structures are compared with conventional DMG FinFET to detect the possible effects of SHE on DC characteristics and thermal parameters. The drop rates of ON current (ION), Off-current (IOFF), Maximum transconductance (gm,max), ION/IOFF ratio, and Drain-induced barrier lowering (DIBL) are calculated to get the precise results. For extensive thermal reliability analysis, the two main distinguishing parameters lattice temperature and thermal resistance are also calculated and their dependency with gate/drain bias and operating temperature are also explored. Comparison between thin and thick BOX devices aimed at distinguishing possible effects of SHE on BOX thickness variation. The result shows that the SHE greatly improves ION/IOFF ratio by 220.8% in gate underlap structure due to large reduction in leakage current. Although lattice temperature is higher in gate overlap structure but thermal resistance decreases by 53.6 % due to its high ON current. Using high-k dielectric BOX materials, small improvement in device SHE characteristics is also accomplished.

Hetero-Interfacial Thermal Resistance Effects on Device Performance of Stacked Gate-All-Around Nanosheet FET

This article reports that Hetero-interfacial-thermal resistance (HITR) due to phonon scattering and weak electron–phonon coupling at hetero-interfaces, can impact stacked Si gate-all-around (GAA) nanosheet field effect transistor (NSHFET) self-heating effect (SHE) and reliability. We have investigated the HITR of Si/SiO2 and Si/metal-silicides on SHE of vertically stacked Si GAA NSHFET. Our simulation predictions reveal that a very noticeable effect of the HITR of Si/ M0 at front end of line (FEOL) and back end of line (BEOL) interface (FEOL/BEOL) is that the hot-spot location is shifted into the channel away from drain depletion region, which affects the device SHE and degrades device performance. The impact of nanosheet width ( ${W}_{NSH}$ ) and sheets stacking number ( ${N}$ ) on device SHE and drive current degradation with and without HITR effect are also studied. It is revealed that wider nanosheets with lower HITR can be a better device design choice for heat mitigation in high performance logic transistors.

Ambient Temperature-Induced Device Self-Heating Effects on Multi-Fin Si CMOS Logic Circuit Performance in N-14 to N-7 Scaled Technologies

We have studied the impact of thermal contact resistance (TCR) ( ${R}_{\text {th}}$ ) and within-chip ambient temperature ( ${T}_{A}$ ) on the device self-heating effect (SHE) and its effect on transient and steady-state performance of Si 3-Fin FinFET-based CMOS inverter (from N-14 to N-7 technologies) using coupled hydrodynamic-thermodynamic (HD-TH) mixed-mode simulations. The effect of the load capacitance ( ${C}_{L}$ ) on device lattice temperature ( ${T}_{L}$ ) and its impact on propagation delay ( ${t}_{\text {pd}}$ ) of the targeted CMOS inverter circuit are analyzed. The impact of technology scaling on SHE of inverter and its effect on circuit performance is also studied. We investigated the SHE in the 3-Fin FinFET-based ring oscillator (RO) and estimated the stage delay and frequency of oscillations. Our simulation results revealed that within-chip ${T}_{A}$ and ${R}_{\text {th}}$ of gate, source, and drain ( ${R}_{\text {th},\text {GSD}}$ ) have significant effect on the logic circuit performance in terms of degradation of noise margin (NM), inverter gain ( $\vert {g}_{\text {max}}\vert $ ), and increase in ${t}_{\text {pd}}$ due to SHE from N-14 to N-7 technologies.

1230 V β-Ga2O3 trench Schottky barrier diodes with an ultra-low leakage current of <1 μA/cm2

β-Ga2O3 vertical trench Schottky barrier diodes (SBDs) are realized, demonstrating superior reverse blocking characteristics than the co-fabricated regular SBDs. Taking advantage of the reduced surface field effect offered by the trench metal-insulator-semiconductor structure, the reverse leakage current in the trench SBDs is significantly suppressed. The devices have a higher breakdown voltage of 1232 V without optimized field management techniques, while having a specific on-resistance (Ron,sp) of 15 mΩ cm2. An ultra-low leakage current density of <1 μA/cm2 is achieved before breakdown, the lowest among all reported Ga2O3 Schottky barrier diodes. Fast electron trapping and slow de-trapping near the Al2O3/Ga2O3 interface are observed by repeated C-V measurements, which show an interface state ledge and positive shifts of flat-band voltages with increasing voltage stress. By comparison between pulsed and DC measurements, the device self-heating effect and the trapping effect are uncoupled. It is found that the trapping effect at the trench sidewall affects the on-resistance of the trench SBDs, even under pulsed conditions. With reduced trapping effect and better field management technique, the trench SBDs could further harvest the promising material properties of β-Ga2O3.

Ambient Temperature-Induced Device Self-Heating Effects on Multi-Fin Si n-FinFET Performance

Device self-heating effects (SHEs) in nonplanar Si MOS transistors such as fin field-effect transistors (FinFETs) and nanowire FETs have become a serious issue in designing well-tempered CMOS devices for future logic nodes. The device thermal contact resistances are strongly influenced by both the ambient temperature and within device lattice temperature. The ambient heat energy coupling through the thermal contact resistances will strongly impact device SHE in FinFETs due to increase in the surface-to-volume ratio of confined geometry thin Si Fin. In this paper, we report a 3-D quantum-corrected electrothermal numerical device analysis involving a coupled hydrodynamic and thermodynamic transport models for a target Si 3-Fin bulk n-FinFET. The numerical device simulations quantitatively predicted the impact of ambient and electrical contact temperatures on device short-channel effect immunity and performance. The simulation parameters are calibrated with the state-of-the-art Si FinFET measurement data from the literature. Our numerical simulation findings establish the phenomena of ambient temperature-induced device SHE on Si n-FinFETs performance for sub-14-nm technology nodes. The simulation predictions establish the fact that the thermal contact resistances and the within-chip ambient temperature ( ${T}_{A}$ ) have adverse effects on device lumped thermal resistance ( ${R}_{\text {th,eff}}$ ) and performance metrics. Finally, we have numerically analyzed the FinFET design solutions (tapered source and drain regions) to improve the tolerance against the ambient temperature-induced SHE.

An analytical MOSFET breakdown model including self-heating effect

This paper presents an analytical breakdown model including self-heating effect (SHE) for NMOSFET devices. Model evaluation is taken for a wide ambient temperature range, from room temperature to 200°C. It is found that the device self-heating effect is suppressed when ambient temperature is increased. In addition, our results suggest that the conventional MOSFET breakdown model without considering the self-heating effect can overestimate the breakdown characteristics for the short-channel devices.

Thermal effects in HBT emitter resistanceextraction

It is shown that device self-heating effects introduce a significant error in the determination of emitter resistance in AlGaAs-GaAs HBTs by the common technique of extrapolating 1/g/sub m/ against 1/l/sub c/ (where g/sub m/ is the observed device transconductance). An approximate expression for the error is given, and an improved technique for R/sub e/ extraction is presented.