Device Model Parameters Research Articles

A compact model of substrate resistance for deep sub-micron gate grounded NMOS electrostatic discharge protection device

The current controlled voltage source model of substrate parasitic resistance of deep sub-micron electrostatic discharge protection device is optimized by considering the effect of conductance modulation. A compact macro-model of substrate resistance is presented according to the characteristics of lightly doped bulk substrate and heavily doped substrate with a lightly doped epitaxial layer, which is scalable with the layout dimension. The experimental model parameters of devices with various spaces between source and substrate diffusion can be extracted by device simulation. The breakdown behavior of gate grounded negative-channel metal oxide semiconductor shows the effectiveness of this method. In the meantime, the simulation time-consuming of the compact model is only 7% that of the device simulation software.

Transient Response of Injection-Locked Active Antenna Arrays

An active antenna array was developed using elements based on a two-port microstrip patch. This topology, being relatively tolerant of device model parameters, is suitable for translating to millimeter-wave frequencies, with monolithic microwave integrated circuit (MMIC) realization. While many such circuits have been reported, the transient response to an external injection-locking signal has been investigated at circuit level for the first time through simulations. It is seen from these simulations that some of the circuits earlier reported will be difficult to use in practice. A modified approach to achieve injection locking is demonstrated experimentally.

Parallel Genetic Algorithm for Intelligent Model Parameter Extraction of Metal-Oxide-Semiconductor Field Effect Transistors

Equivalent circuit model of semiconductor devices associated with a set of optimized parameters currently plays a central role in the circuit design and semiconductor manufacturing communities. An intelligent model parameter extraction system that simultaneously integrates evolutionary and numerical optimization techniques for optimal characterization of sub-100 nm metal-oxide-semiconductor field effect transistors (MOSFETs) has recently been advanced [1]. In this article, to accelerate the extraction process, parallelization of the genetic algorithm (GA) for the intelligent model parameter extraction system of MOSFETs is developed. The GA implemented in the extraction system is mainly parallelized with a diffusion scheme on a PC-based Linux cluster with message passing interface libraries. Parallelization of GA is governed by various factors, which affect the quality of extracted parameters and its computational efficiency. The result obtained in this study shows that the diffusion GA is superior to an isolated GA, and the superiority of the diffusion GA becomes significant when the number of MOSFETs to be optimized is increased. Theoretical estimation and preliminary numerical implementation of parallel GA show that there exist an optimal number of processors with respect to the number of devices to be extracted. Benchmark results, such as speedup and efficiency including accuracy of extraction are presented and discussed for different sets of realistic multiple sub-100 nm devices to show the robustness and efficiency of the method. Practical implementation of the parallel GA approach benefits the engineering of device model parameter extraction in nowadays semiconductor manufacturing industry.

Identifying Model Parameters of Semiconductor Devices Using Optimization Techniques

The optimization is an indispensable tool for extracting the parameters of any complicated models. Hence, advanced optimization techniques are also necessary for identifying the model parameters of semiconductor devices because their current models are very sophisticated (especially the BJT and MOSFET ones). The equations of such models contain typically one hundred parameters. Therefore, the measurement and particularly identification of the full set of the model parameters is very difficult. In the paper, an optimization method is presented which is applicable for the identifications of very complicated models using a relatively small number of iterations. The algorithm has been implemented into the original software tool C.I.A. (Circuit Interactive Analyzer) to its static and dynamic analysis modes. Therefore, the optimization is able to identify both direct-current and capacitance models of semiconductor devices. The process is demonstrated with various transistors.

An automatic parameter extraction technique for advanced CMOS device modeling using genetic algorithm

We in this paper present an computational intelligence technique to extract semiconductor device model parameters. This solution methodology is based on a genetic algorithm (GA) with an exponential type weight function, renew operator, and adaptive sampling scheme. The proposed approach automatically extracts a set of complete parameters with respect to a specified compact model, such as a BSIM model for deep-submicron and nanoscale complementary metal-oxide-semiconductor (CMOS) devices. Compared with conventional artificial step-by-step fitting approaches, the proposed extraction methodology automatically tracks the shape variation of current–voltage ( I– V) curves and examines the first derivative of I– V curves; therefore, highly accurate results can be obtained directly. Applying the renew operator will keep the evolutionary trend improving by removing the individuals without mainly features. The sampling strategy will speed up the evolution process and still maintain the extraction accuracy in a reasonable range. A developed prototype is successfully applied to extract model parameter of N- and P-metal-oxide-semiconductor field effect transistors (MOSFETs). This optimization method shows good physical accuracy and computational performance, and provides an alternative for optimal device modeling and circuit design in nanodevice era. Genetic algorithm based automatic model parameter extraction bridges the communities between circuit design and chip fabrication; in particular, it will significantly benefits design of system-on-a-chip.

Dynamic stress-induced high-frequency noise degradations in nMOSFETs

Device parameter shifts in nMOSFETs subject to inverter-like dynamic voltage stress are examined experimentally. Model equations to relate high-frequency noise to device parameters are given. Dynamic stress-induced degradations in high-frequency noise performance of 0.16 μm nMOSFETs are investigated. Good agreement between the analytical predictions and experimental data is obtained. Noise performance of a Gilbert mixer is evaluated using Cadence SpectreRF simulation with the measured device model parameters.

Technology portable analytical model for DSM CMOS inverter delay estimation

A closed form expression to accurately estimate the delay of a CMOS deep submicron (DSM) inverter is presented. This model does not depend on extracted or fitting parameters. Instead it depends on device model parameters, and hence becomes portable across technology generations. Delay analytical model verification was performed against Spectre simulations using a BSIM3v3 model for a wide range of device sizes, capacitive loads and transition times. Model portability was tested across three DSM technologies: UMC's 0.13 μm and TSMC's 0.18 μm and 0.25 μm. The model exhibits high accuracy with average and maximum errors of about 2.3% and 10% compared to simulation.

Extraction method for polycrystalline TFT above and below threshold model parameters

A procedure is presented to extract above and sub-threshold model parameters in polysilicon TFTs. It is based on the integration of the experimental data current, which has the advantage of reducing the effects of experimental noise. This method is applied to the linear and saturation regions for the above-threshold regime and allows the extraction of all the above-threshold and sub-threshold parameters. We already presented a unified extraction method for the above threshold parameters of a-Si:H and polysilicon TFTs, where the above-threshold regime the mobility is modeled as a function of the gate voltage to a power. An integration procedure is used to extract the device model parameters. In this paper, we complete the extraction procedure to cover all the device operation regions, that is the sub-threshold and above-threshold regimes. The extraction procedure provides in addition the possibility of monitoring the crystallization process of a-Si:H TFTs into polysilicon, which has become a widely used process of fabricating low temperature polysilicon TFTs. The process of polycrystallization manifests itself by a variation and change in sign of one of the model parameters. Extracted parameters can be correlated to input parameters required by AIM-Spice circuit simulator for device modeling. The accuracy of the simulated curves using the extracted parameters is verified with measurements.

Bias correction and yield optimization of MMICs with external digital control

AbstractA new methodology for yield optimization of integrated circuits is presented. We propose a dc external control scheme which performs on‐line estimation of the active device model parameters and proper correction of the bias point. Design of a 2.5 Gbit/s front‐end amplifier has been performed, and a strong yield improvement has been found. © 2001 John Wiley & Sons, Inc. Microwave Opt Technol Lett 31: 134–137, 2001.

Improved analytical modeling of polysilicon depletion in MOSFETs for circuit simulation

Polysilicon gate depletion is an important effect that degrades the circuit performance of deep submicron standard CMOS technologies. A new approach to analytically modeling the polysilicon depletion effect on drain current and transconductances as well as node charges and transcapacitances is presented. The model is based on a clear physical analysis of the charges in the MOS transistor structure. Using the modeling framework and the fundamental variables of the EKV MOS transistor model formalism and that of the related charges models, a continuous model is achieved that is valid in all operating regions from weak inversion to strong inversion and from non-saturation to saturation. The asymptotic behavior of the transcapacitances is improved with respect to former model formulations. Only the doping concentration in the polygate is used in addition to the other physical device model parameters. The model shows excellent results in comparison with a surface potential based numerical model and 2D numerical device simulation. The model is efficient for circuit simulation and is further practical for analog circuit design.

Extraction of Passive Device Model Parameters Using Genetic Algorithms

The extraction of model parameters for embedded passive components is crucial for designing and characterizing the performance of multichip module (MCM) substrates. In this paper, a method for optimizing the extraction of these parameters using genetic algorithms is presented. The results of this method are compared with optimization using the Levenberg-Marquardt (LM) algorithm used in the HSPICE circuit modeling tool. A set of integrated resistor structures are fabricated, and their scattering parameters are measured for a range of frequencies from 45 MHz to 5 GHz. Optimal equivalent circuit models for these structures are derived from the s-parameter measurements using each algorithm. Predicted s-parameters for the optimized equivalent circuit are then obtained from HSPICE. The difference between the measured and predicted s-parameters in the frequency range of interest is used as a measure of the accuracy of the two optimization algorithms. It is determined that the LM method is extremely dependent upon the initial starting point of the parameter search and is thus prone to become trapped in local minima. This drawback is alleviated and the accuracy of the parameter values obtained is improved using genetic algorithms.

DC model for BiMOS structure and its adaptation to a circuit simulation environment

The objective was to develop a model that can accurately describe the hybrid-mode operation of deep submicron LDD pMOSFETs in a circuit simulation environment. The device threshold voltage, various current components, transconductance, and output conductance are extracted experimentally, modelled analytically, and adapted to meet the circuit simulation requirements. The latter necessitates that the model equations, together with their derivatives, be continuous. The effects of independently biasing the source, drain, gate, and body potentials on the device currents and parameters are highlighted. A critical comparison between the presented model XSIM and HSPICE is made. The results show that unlike HSPICE, where the MOSFET and the bipolar device embedded in the structure have to be simulated as two entities, the suggested model describes the composite structure as a single entity and predicts its behaviour accurately for a range of different channel lengths based on a single set of process and device model parameters.

Direct sampling methodology for statistical analysis of scaled CMOS technologies

The continued scaling of CMOS technologies introduces new difficulties to statistical circuit analysis and invalidates many of the methodologies developed earlier. The analysis of device parameter distributions reveals multiple sources of parameter correlations, some of which exhibit mutually opposing trends. We found that applying principal component analysis (PCA) to such heterogeneous statistical data may lead to confounding of data and result in underestimation of the total parameter variance. This imposes considerable constraints on the use of several methods of statistical circuit analysis based on PCA. Also the highly nonlinear relationships between the device parameters become more pronounced and cannot be approximated as linear even in the differential range. As a result, the response surface models based on the linear expansion of the performance variable around the nominal point of the device model parameters may lead to significant prediction errors. To address these difficulties, we propose a conceptually simple and accurate approach of direct sampling that treats the extracted SPICE parameter sets and their physical locations as an inseparable set and thus bypasses the dangerous stage of statistical inferences. We illustrate the methodology by applying it to the statistical analysis of a production CMOS process.

Analysis of microwave generation by field emitted electrons moving in crossed electric and magnetic fields

A new microwave generating device is proposed and analysed theoretically. The device is based on the controlled motion of field emission (FE) electrons in a vacuum working space subject to crossed electric E and magnetic B fields. A cylindrical capacitor configuration is considered, the symmetry of the arrangement being cylindrical around the B axis whilst the radial electric field is applied between two co-axial surfaces. The electrons obtained from a FE cathode placed between these surfaces are shown to move on a cycloid-like trajectory. The high acceleration values of the electrons produced by the fields lead to significant electromagnetic radiation in the GHz range. The emitted power per electron and the frequency spectrum as functions of device model parameters are computed and several design suggestions are drawn.

Some aspects of application of the two parameter SEU model

The influence of the projectile type, pion production in the nucleon-nucleon interaction inside the nucleus and direction of the beam incidence on SEU cross section for an Intel 2164A microcircuit is investigated in the framework of the two parameter model. Model parameters for devices investigated recently are reported. Optimum proton energies for determination of model parameters are proposed.

PastA—the characterization of the inherent fluctuations in the fabrication process for circuit simulation

AbstractFor worst‐case analysis, Monte Carlo analysis, yield optimization and design centring, the variations and correlations of the device model parameters in the electrical circuit simulation are of fundamental significance. This paper describes a method for the complete characterization of the inherent fluctuations in the fabrication process for the simulation in IC design. the emphasis is placed on analogue simulation owing to the complex connections between circuit design and technology and the multitude of devices with correlated parameters; nevertheless, statistical requirements for digital simulation can be fully covered.This characterization works with all technologies whether CMOS, BiCMOS or bipolar. the prerequisites are accurate nominal device model parameters for the circuit simulation and information about fabrication statistics, e.g. process control monitor measurements. A new approach with connection coefficients for the calculation of the correlation coefficients is presented. Dependent parameters can be easily defined through a connection hierarchy. With the presented approach the variations and correlations of model parameters for simulation can be generated from estimates or measurements of the fabrication process. Based on sensitivity analysis, the variations and correlations of design objectives can be estimated. This enables the designer to do circuit analysis and optimization (limit parameters, worst‐case distances) as well as Monte Carlo analysis.

Large current and low voltage switching devices using HTS thin film

A high temperature superconducting (HTS) thin film has a potential to control large currents using its transition between a superconducting state and a normal conducting state. In this paper an equivalent circuit model of a HTS thin film is presented to design a power conditioning circuit as an inverter which can handle large currents at voltages less than 1 V. Device model parameters of a HTS thin film were determined by comparing quenching characteristics calculated by a circuit simulation program (PSpice) with those measured experimentally. A temporal behavior of resistance of the HTS thin film quenched by a self-current which was simulated using the model were compared with experimental results. An inverter circuit using the HTS thin film switched thermally is designed and the characteristic of a switching operation with a photovoltaic cell is also shown.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A physical and computationally efficient methodology for statistical circuit simulation in bipolar technologies

A methodology for statistical circuit simulation in advanced bipolar technologies is developed based on a novel IC TCAD system consisting of the semi-numerical mixed-mode device/circuit simulator MMSPICE with its parameter evaluator SUMM. The system reliably and efficiently relates device/circuit performance directly to measurable fabrication-process parameters since MMSPICE/SUMM implicitly accounts for physical correlations among device model parameters and does not rely on optimization (i.e. parameter extraction). The computational efficiency permits use of a simple Monte Carlo technique involving random generation of process parameters for the statistical simulation. The utility of the methodology is demonstrated by predicting IC parametric yields and statistical device/circuit performance correlations from specified fluctuations of process parameters in an actual bipolar technology.

Insulated gate bipolar transistor (IGBT) modeling using IG-SPICE

A physics-based model for the insulated gate bipolar transistor (IGBT) is implemented into the widely available circuit simulation package IG-SPICE. Based on analytical equations describing the semiconductor-physics, the model accurately describes the nonlinear junction capacitances, moving boundaries, recombination, and carrier scattering, and effectively predicts the device conductivity modulation. In this paper, the procedure used to incorporate the model into IG-SPICE and various methods necessary to ensure convergence are described. The effectiveness of the SPICE-based IGBT model is demonstrated by investigating the static and dynamic current sharing of paralleled IGBTs with different device model parameters. The simulation results are verified by comparison with experimental results. >

Measurement and modeling of self-heating in SOI nMOSFET's

Self-heating in SOI nMOSFET's is measured and modeled. Temperature rises in excess of 100 K are observed for SOI devices under static operating conditions. The measured temperature rise agrees well with the predictions of an analytical model and is a function of the silicon thickness, buried oxide thickness, and channel-metal contact separation. Under dynamic circuit conditions, the channel temperatures are much lower than predicted from the static power dissipation. This work provides the foundation for the extraction of device modeling parameters for dynamic operation (at constant temperature) from static device characterization data (where temperature varies widely). Self-heating does not greatly reduce the electromigration reliability of SOI circuits, but might influence SOI device design, e.g., requiring a thinner buried oxide layer for particular applications and scaled geometries. >