Device Instability Research Articles

Isolating Degradation Mechanisms in Mixed Emissive Layer Organic Light-Emitting Devices.

Degradation in organic light-emitting devices (OLEDs) is generally driven by reactions involving excitons and polarons. Accordingly, a common design strategy to improve OLED lifetime is to reduce the density of these species by engineering an emissive layer architecture to achieve a broad exciton recombination zone. Here, the effect of exciton density on device degradation is analyzed in a mixed host emissive layer (M-EML) architecture which exhibits a broad recombination zone. To gain further insight into the dominant degradation mechanism, losses in the exciton formation efficiency and photoluminescence (PL) efficiency are decoupled by tracking the emissive layer PL during device degradation. By varying the starting luminance and M-EML thickness, the rate of PL degradation is found to depend strongly on recombination zone width and hence exciton density. In contrast, losses in the exciton formation depend only weakly on the recombination zone, and thus may originate outside of the emissive layer. These results suggest that the lifetime enhancement observed in the M-EML architectures reflects a reduction in the rate of PL degradation. Moreover, the varying roles of excitons and polarons in degrading the PL and exciton formation efficiencies suggest that kinetically distinct pathways drive OLED degradation and that a single degradation mechanism cannot be assumed when attempting to model the device lifetime. This work highlights the potential to extract fundamental insight into OLED degradation by tracking the emissive layer PL during lifetime testing, while also enabling diagnostic tests on the root causes of device instability.

Evolution of Defect Structures and Deep Subgap States during Annealing of Amorphous In-Ga-Zn Oxide for Thin-Film Transistors

Amorphous indium gallium zinc oxide ($a$-IGZO) has drawn considerable interest as a channel material in flexible thin-film transistors (TFTs), to replace amorphous-Si-based TFTs, but $a$-IGZO-based TFTs show environment-dependent instability in threshold voltage. Investigating the variation of defect structures and subgap states with post-annealing temperature, this study reveals that the excess oxygen atoms surrounding cations or cation-vacancy-related defect clusters give rise to the instability. These results open a route to understanding the physical origin of device instability, and offer a feasible approach to tailoring such defects for practical applications.

Stability Analysis of All-Inkjet-Printed Organic Thin-Film Transistors

All-inkjet-printed organic thin-film transistors take advantage of low-cost fabrication and high compatibility to large-area manufacturing, making them potential candidates for flexible, wearable electronics. However, in real-world applications, device instability is an obstacle, and thus, understanding the factors that cause instability becomes compelling. In this work, all-inkjet-printed low-voltage organic thin-film transistors were fabricated and their stability was investigated. The devices demonstrate low operating voltage ( 105). Several aspects of stability were investigated, including mechanical bending, shelf life, and bias stress. Based on these tests, we find that water molecule polarization in dielectrics is the main factor causing instability. Our study suggests use of a printable water-resistant dielectric for stability enhancement for the future development of all-inkjet-printed organic thin-film transistors.

Measurement considerations for evaluating BTI effects in SiC MOSFETs

In this paper, we review the phenomenon of bias-temperature instability (BTI) in SiC MOS devices, with an emphasis on the effects of metrology. The complex behavior of the charge trapping mechanism responsible for VT instability requires careful consideration of measurement conditions and precise control of the associated parameters to produce meaningful results. Preconditioning the devices to be tested, as well as making faster measurements, will elicit the truest response. Any bias interruption or delay between stressing and measurement will produce a large deterioration in the original VT drift caused by the stressing, though this can be effectively counteracted by briefly reapplying the stress bias before measurement.

First ten years of active metamaterial structures with “negative” elements

Almost ten years have passed since the first experimental attempts of enhancing functionality of radiofrequency metamaterials by embedding active circuits that mimic behavior of hypothetical negative capacitors, negative inductors and negative resistors. While negative capacitors and negative inductors can compensate for dispersive behavior of ordinary passive metamaterials and provide wide operational bandwidth, negative resistors can compensate for inherent losses. Here, the evolution of aforementioned research field, together with the most important theoretical and experimental results is reviewed. In addition, some very recent efforts that go beyond idealistic impedance negation and make use of inherent non-ideality, instability, and non-linearity of realistic devices, are highlighted. Finally, a very fundamental, but still unsolved issue of common theoretical framework that connects causality, stability, and non-linearity of networks with negative elements is stressed.

Simulation of the Spiking Neural Network based on Practical Memristor

In order to gain a better understanding of the brain and explore biologically-inspired computation, significant attention is being paid to research into the spike-based neural computation. Spiking neural network (SNN), which is inspired by the understanding of observed biological structure, has been increasingly applied to pattern recognition task. In this work, a single layer SNN architecture based on the characteristics of spiking timing dependent plasticity (STDP) in accordance with the actual test of the device data has been proposed. The device data is derived from the Ag/GeSe/TiN fabricated memristor. The network has been tested on the MNIST dataset, and the classification accuracy attains 90.2%. Furthermore, the impact of device instability on the SNN performance has been discussed, which can propose guidelines for fabricating memristors used for SNN architecture based on STDP characteristics.

Nonlinear mechanics of electrically actuated microplates

The three-dimensional nonlinear mechanics and pull-in characteristics of a microplate-based microelectromechanical system (MEMS) are investigated via a multi-degree freedom energy-based technique where the in-plane and out-of-plane motions are retained in the modelling and simulations; the deformable microplate is modelled using the Kirchhoff's plate theory in conjunction with von Kármán nonlinear strains, and it is assumed to be fully clamped at all the edges; an electrical field in the form of a combination of DC and AC voltages is applied to the deformable electrode of microplate-type. The modified couple stress theory is employed to model the small-size effects. The potential energy with size-dependent characteristics, together with the deformable microplate's kinetic energy, is formulated as functions of the displacements and mechanical and geometric parameters of the system. These energy terms, along with the Rayleigh energy dissipation and the electrical potential energy, are inserted into Lagrange's equations to derive the discretised model of the microplate-based MEMS consisting of three sets of second-order coupled reduced-order models for the in-plane and out-of-plane motions. Numerical simulations are conducted for both static and dynamic responses of the MEMS device. The numerical simulations have been performed via use of the pseudo-arc-length continuation technique in conjunction with backward-differentiation-formula (BDF) (for the nonlinear analysis); the Floquet theory is used for stability analysis. An eigenvalue extraction is employed for the linear analysis. Results are shown through DC voltage-deformation and AC frequency-motion diagrams in order to highlight the motion characteristics as well as pull-in instability of the microplate-based MEMS device.

Stable MoS2 Field‐Effect Transistors Using TiO2 Interfacial Layer at Metal/MoS2 Contact (Phys. Status Solidi A 12∕2017)

As the physical scaling of traditional silicon CMOS devices is gradually approaching its physical limit, molybdenum disulfide (MoS2) having a two-dimensional atomic-layered structure has attracted significant interest as a new emerging semiconductor channel material. However, relatively poor device performance and instability during device operation with MoS2 are of great concern. The bonding mismatch between different materials causes interface issue and instability. Hence, solving this interface issue between metal electrodes and MoS2 is critical. Therefore, here (article No.201700534), a thin titanium dioxide (TiO2) insulating film as a buffer layer has been sandwiched between the metal electrode (Ti) and MoS2. The TiO2 insulating film was used among the various materials since it is well-matched with both Ti and MoS2 electrically. As a result, higher performance, and longer and stable operation were observed in MoS2 based transistors.

Analysis of the Forward I–V Characteristics of Al-Implanted 4H-SiC p-i-n Diodes with Modeling of Recombination and Trapping Effects Due to Intrinsic and Doping-Induced Defect States

In this paper, the impact of silicon carbide intrinsic defect states, such as Z1/2 and EH6/7 centers, on the forward current–voltage curves of aluminum (Al)-implanted 4H-SiC p-i-n diodes is investigated by means of a physics-based device simulator. During the simulations, an explicit carrier trap effect due to an electrically active defect concentration produced by the Al+ ion implantation process in the anode region was also taken into account. The obtained current–voltage characteristics are compared with those measured experimentally for several samples at different current levels. It is found that intrinsic defect densities as high as the epilayer doping may lead to undesirable device properties and instability of the forward bias behavior. The diode ideality factor and the series resistance increase with the increase of defects and could be controlled by using high-purity epi-wafers. Furthermore, due to their location in the bandgap and capture cross-sections, the impact of Z1/2 centers on the device electrical characteristics is more severe than that of EH6/7 centers.

Conscious sedation for transcatheter implantation of atrial septal occluders with two- and three-dimensional transoesophageal echocardiography guidance - a feasibility and safety study.

General anaesthesia may have negative impact on patient mortality and morbidity, as well as overall procedure costs, in atrial septal occluder (ASO) implantation. We sought to evaluate the safety, efficacy, and feasibility of conscious sedation for transcatheter implantation of ASOs. A total of 122 patients referred for transcatheter implantation of ASO were included. Mean patient age was 51 ± 15 years, and 43 (35%) patients were male. The initial dose of midazolam was 2 mg and fentanyl dose was 25 μg. Additional doses of midazolam and fentanyl were administered, if necessary. Patient responsiveness was assessed every 10 min, and the sedatives doses were titrated in order not to exceed grade 3 sedation in the Ramsey scale. Atrial septal occluders were successfully implanted in the majority of patients (98.4%). In two (1.6%) cases the proce-dure failed because of too small patent foramen ovale (PFO) diameter (n = 1, 0.8%) or device instability (n = 1, 0.8%). The mean duration of procedure was 47.6 ± 28.4 min and was similar for ASD and PFO closure (p = 0.522). The overall mean dose of midazolam was 4.7 ± 2.2 mg (63.9 ± 32.5 μg/kg) and fentanyl was 30.0 ± 11.9 μg (0.43 ± 0.17 μg/kg). Median entrance dose of radiation at the patient plane was 25 (interquartile range: 16-57) mGy, and did not differ between ASD and PFO procedures (p = 0.614). The majority of patients were free of complications (91.0%). The following early complications were observed: transient ischaemic attack (n = 2, 1.6%), supraventricular arrhythmias (n = 4, 3.3%), left atrial thrombus formation (n = 1, 0.8%), symptomatic bradycardia (n = 1, 0.8%), and femoral venous bleeding (n = 5, 4.1%). After mean follow-up of 386 days residual shunt was observed in eight (6.6%) patients. Conscious sedation for transcatheter implantation of ASO is a feasible, safe, and efficient technique, allowing successful PFO and ASD closure in the majority of patients.

Efficient Suppression of Defects and Charge Trapping in High Density In-Sn-Zn-O Thin Film Transistor Prepared using Microwave-Assisted Sputter.

Amorphous oxide semiconductor-based thin film transistors (TFTs) have been considered as excellent switching elements for driving active-matrix organic light-emitting diodes (AMOLED) owing to their high mobility and process compatibility. However, oxide semiconductors have inherent defects, causing fast transient charge trapping and device instability. For the next-generation displays such as flexible, wearable, or transparent displays, an active semiconductor layer with ultrahigh mobility and high reliability at low deposition temperature is required. Therefore, we introduced high density plasma microwave-assisted (MWA) sputtering method as a promising deposition tool for the formation of high density and high-performance oxide semiconductor films. In this paper, we present the effect of the MWA sputtering method on the defects and fast charge trapping in In-Sn-Zn-O (ITZO) TFTs using various AC device characterization methodologies including fast I-V, pulsed I-V, transient current, low frequency noise, and discharge current analysis. Using these methods, we were able to analyze the charge trapping mechanism and intrinsic electrical characteristics, and extract the subgap density of the states of oxide TFTs quantitatively. In comparison to conventional sputtered ITZO, high density plasma MWA-sputtered ITZO exhibits outstanding electrical performance, negligible charge trapping characteristics and low subgap density of states. High-density plasma MWA sputtering method has high deposition rate even at low working pressure and control the ion bombardment energy, resulting in forming low defect generation in ITZO and presenting high performance ITZO TFT. We expect the proposed high density plasma sputtering method to be applicable to a wide range of oxide semiconductor device applications.

Fast and slow transient charging of Oxide Semiconductor Transistors

The comprehension of the governing mechanism which affects device instability is one of the most important requirements for the formation of reliable oxide-thin film transistors (TFTs). However, a quantitative analysis of the dominant mechanism of device instability, which stems from charge trapping induced by defects at the oxide semiconductor interface as well as in its bulk, has not yet been systematically performed. In this study, we examined subgap states, charge-transport dynamics, and various trap characteristics of oxide TFTs by multi-frequency C–V, pulse I–V, and transient current methods to achieve a comprehensive understanding of carrier transport and charge trapping mechanisms. We found that the charge trapping behavior of the tested amorphous InHfZnO (a-IHZO) TFT follows a multi-trapping mechanism, such as temperature-independent fast transient charge trapping by resonant drift of the injected electron and temperature-dependent slow transient charge trapping by charge transport from occupied to unoccupied traps. Understanding fast charging and slow charging described in this study can help to understand the root cause of device instability of oxide TFTs and ultimately improve stability and reliability characteristics.

Self‐Assembly Atomic Stacking Transport Layer of 2D Layered Titania for Perovskite Solar Cells with Extended UV Stability

AbstractA novel atomic stacking transporting layer (ASTL) based on 2D atomic sheets of titania (Ti1−δO2) is demonstrated in organic–inorganic lead halide perovskite solar cells. The atomically thin ASTL of 2D titania, which is fabricated using a solution‐processed self‐assembly atomic layer‐by‐layer deposition technique, exhibits the unique features of high UV transparency and negligible (or very low) oxygen vacancies, making it a promising electron transporting material in the development of stable and high‐performance perovskite solar cells. In particular, the solution‐processable atomically thin ASTL of 2D titania atomic sheets shows superior inhibition of UV degradation of perovskite solar cell devices, compared to the conventional high‐temperature sintered TiO2 counterpart, which usually causes the notorious instability of devices under UV irradiation. The discovery opens up a new dimension to utilize the 2D layered materials with a great variety of homostructrual or heterostructural atomic stacking architectures to be integrated with the fabrication of large‐area photovoltaic or optoelectronic devices based on the solution processes.

Short-Term Instability of the Post-Programmed Resistance State in HfO2-Based Rram

Filamentary oxide-based Resistive Random Access Memories (RRAM) are strong candidates for future Non-Volatile Memory (NVM) because of their simple structure, ease of fabrication, high-speed, high density and scalability [1]. However, the reliance on a highly localized nanometer scale conductive filament through an insulator leads to serious challenges such as the stochastic nature of the resistance state and the stochastic fluctuation of the state’s resistance value after it is programmed. A potentially promising solution to the resistance state control issue is “program-verify”, which checks to make sure that the desired resistance value is achieved before each program operation is considered finished. However, recent reports in the literature suggest that this approach does not work because of post-programming relaxation of the filament [2, 3]. This result is truly problematic and deserves closer scrutiny to understand the root cause. In this work, we investigate in detail the instability of the post-programmed state of HfO2-based RRAM devices using a newly developed programming setup. Our novel Compliance-free Ultra-short Smart Pulse Programming (CUSPP) method supports program-verify operation, automatic cycling of SET/RESET states at high rates, and continuous resistance state monitoring with nanosecond measurement time resolution. We investigated the short-term instability of HfO2-based RRAM devices during programming in the time range of 100 ns to 1 s. Our measurements demonstrate conclusively that it is fluctuation, not relaxation, that significantly degrades the effectiveness of the program-verify approach. While this new insight is valuable for understanding the problem as well as searching for a solution, we uncovered additional troubling details. We observe that the occurrence probability (frequency) of these fluctuations initially decreases (over 100 μs) before reaching a non-zero steady state value that never vanished over the time duration of our study. Even more alarming is the observation that the fluctuation amplitude never decreases within the same time duration. These observations indicate that that techniques such as delay reading or averaging will not relieve this fundamental problem [4].

Device Instability of ReRAM and a Novel Reference Cell Design for Wide Temperature Range Operation

This letter addresses two difficult challenges for transition metal oxide resistive random access memories (ReRAMs)—sensitivity to operation temperature and random fluctuation of resistance value. A careful study of a WO x ReRAM array reveals that these devices are unstable and their read currents fluctuate with time due to random telegraph noise and structure relaxation. Consequently, even after careful programming, the current distribution can broaden with time and tail bit population grows. Furthermore, ReRAM state is sensitive to temperature and a reference cell made of the same device material must be used. Thus, although the broadening of read current distribution may be tolerated by creating a larger RESET/SET memory window, the current fluctuation still makes it impossible to predict the output of the reference cell, leading to array malfunction. This letter investigates the current (resistance) instability in detail and proposes a reference array with a novel trimming method that can stabilize the reference current level. The proposed reference array has very good dc stress reliability as well as wide-range temperature tracking performance from −40 °C to 85 °C.

Microsecond Pulse I\u2013V Approach to Understanding Defects in High Mobility Bi-layer Oxide Semiconductor Transistor

The carrier transport and device instability of amorphous oxide semiconductor devices are influenced by defects that are exponentially distributed in energy, because of amorphous phase channels and front/back interfaces with a large number of sub-gap states. Thus, understanding defects and charge trapping in oxide semiconductor transistors is required for being core device element in reliable production lines. In this paper, we present the transient charging effect, the charge trapping mechanism, and the dynamic charge transport of high-mobility bilayer oxide semiconductor transistors. To this end, we exploited microsecond ramps, pulse ID–VG, transient current, and discharge current analysis methods. The mobility enhancement rate of single HfInZnO (HIZO) and bilayer HfInZnO-InZnO (HIZO-IZO) were 173.8 and 28.8%, respectively, in the charge-trapping-free environment. Transient charge trapping can be classified to temperature insensitive fast charging and thermally activated slow charging with two different trap energies. Insignificant fast transient charging of a bilayer-oxide high-mobility thin film transistor(TFT) can be explained by the low density of sub-gap states in the oxide semiconductor. Understanding defects and transient charging in the oxide semiconductor helps to determine the origin of device instability of oxide TFTs, and finally, to solve this problem.

Scalable Nanowire Photonic Crystals: Molding the Light Emission of InGaN

To date, there have been no efficient semiconductor light emitters operating in the green and amber wavelengths. This study reports on the synthesis of InGaN nanowire photonic crystals, including dot‐in‐nanowires, nanotriangles, and nanorectangles with precisely controlled size, spacing, and morphology, and further demonstrates that bottom‐up InGaN photonic crystals can exhibit highly efficient and stable emission. The formation of stable and scalable band edge modes in defect‐free InGaN nanowire photonic crystals is directly measured by cathodoluminescence studies. The luminescence emission, in terms of both the peak position (λ ≈ 505 nm) and spectral linewidths (full‐width‐half‐maximum ≈ 12 nm), remains virtually invariant in the temperature range of 5–300 K and under excitation densities of 29 W cm−2 to 17.5 kW cm−2. To the best of our knowledge, this is the first demonstration of the absence of Varshni and quantum‐confined Stark effects in wurtzite InGaN light emitters—factors that contribute significantly to the efficiency droop and device instability under high‐power operation. Such distinct emission properties of InGaN photonic crystals stem directly from the strong Purcell effect, due to efficient coupling of the spontaneous emission to the highly stable and scalable band‐edge modes of InGaN photonic crystals, and are ideally suited for uncooled, high‐efficiency light‐emitting‐diode operation.

Negative bias illumination stress instability in amorphous InGaZnO thin film transistors with ITO local conducting buried layer

The investigations on the device instabilities of amorphous InGaZnO thin film transistors (a-IGZO TFTs) with ITO local conducting buried layer (LCBL) under the source/drain region and in the middle of the active channel region have been performed under negative bias and illumination stress. From the increased drain current of a-IGZO with ITO LCBL, one can control the drive current by modulating the length of ITO LCBL without changing the ratio of channel width and length. The reason for the less degradation of a-IGZO TFTs with LCBL under negative bias stress than that of device without LCBL was explained by the fact that ITO LCBL could act to reduce the effective energy barrier and act as a hole damping layer. However, the device degradation of a-IGZO with ITO LCBL under negative bias and illumination stress was more significant than that of one without LCBL due to the electron hole pair generation in ITO layer under illumination.

An acrylated fullerene derivative for efficient and thermally stable polymer solar cells

The continuous microstructure evolution occurring in active layers of polymer-fullerene solar cells is one of the main causes for their device instability. With aim to tackle it, this work developed a new polymerizable fullerene acceptor, [6,6]-phenyl-C61-butyl acrylate (PC61BA). It was found that PC61BA has similar light-absorption properties and HOMO and LUMO energy levels as [6,6]-phenyl-C61-butyric acid methyl ester (PC61BM), and can be converted into insoluble oligomers upon heating at 150 °C. Polymer-fullerene solar cells using poly(3-hexylthiophene) (P3HT) as donor and PC61BA as acceptor exhibited an optimized efficiency of 3.54%, the performance comparable to P3HT/PC61BM cells (optimized efficiency: 3.70%). But, the former possess much better thermal stability than the latter owing to aggregation suppression by the polymerized PC61BA. These results indicate that PC61BA, unlike most previous reported, is a unique polymerizable fullerene derivative that can be used alone as acceptor to achieve both efficient and thermally stable polymer solar cells.

Electrical Stability Impact of Gate Oxide in Channel Implanted SiC NMOS and PMOS Transistors

Operation of SiC MOSFETs beyond 300°C opens up opportunities for a wide range of CMOS based digital and analogue applications. However the majority of the literature focuses only on the optimization of a single type of MOS device (either PMOS or more commonly NMOS) and there is a lack of a comprehensive study describing the challenge of optimizing CMOS devices. This study reports on the impact of gate oxide performance in channel implanted SiC on the electrical stability for both NMOS and PMOS capacitors and transistors. Parameters including interface state density (Dit), flatband voltage (VFB), threshold voltage (VTH) and effective charge (NEFF) have been acquired from C-V characteristics to assess the effectiveness of the fabrication process in realising high quality gate dielectrics. The performance of SiC based CMOS transistors were analyzed by correlating the characteristics of the MOS interface properties, the MOSFET 1/f noise performance and transistor on-state stability at 300°C. The observed instability of PMOS devices is more significant than in equivalent NMOS devices. The results from MOS capacitors comprising interface state density (Dit), flatband voltage (VFB), threshold voltage (VTH) for both N and P MOS are in agreement with the expected characteristics of the respective transistors.