Device Driver Research Articles

An analysis of the impact of network device buffers on packet schedulers through experiments and simulations

Keeping the delay experienced by packets while travelling from a source to a destination below certain thresholds is essential to successfully deliver a number of Internet services nowadays. Most of the packet delay can be usually ascribed to the time spent in the many queues encountered by the packet. In this context, the term bufferbloat has been recently coined to denote the uncontrolled growth of the queuing time due, among others, to the excessive size of the buffers and the attitude of TCP to increase the sending rate until a packet is dropped. In this paper, we focus on the queues employed by the traffic control infrastructure and by the network device drivers. Reducing the queuing time due to the former is the objective of a plethora of scheduling algorithms developed in the past years and referred to as Active Queue Management (AQM) algorithms. Conversely, the impact of the additional queuing in the buffer of the network device driver on performance and on the effectiveness of AQM algorithms has instead received much less attention. In this paper, we report the results of an experimental analysis we conducted to gain a better insight into the impact that network device buffers (and their size) have on performance. We also give an in-depth presentation of Dynamic Queue Limits (DQL), an algorithm recently introduced in the Linux kernel to dynamically adapt the size of the buffers held by network device drivers. The experiments we conducted show that DQL not only enables to reduce the queuing time in the network device buffers, which is essential to ensure the effectiveness of AQM algorithms, but also enables to keep latency stable, which is important to reduce the jitter. In order to faithfully reproduce through simulations the dynamics revealed by the experimental study we conducted, we implemented DQL for the popular ns-3 network simulator. In this paper, we describe the design of such implementation and report the results of a simulation study we conducted to show the ability of the simulator to accurately reproduce the experimental results.

Enabling Realistic Logical Device Interface and Driver for NVM Express Enabled Full System Simulations

Data volumes are drastically increasing, immense information created over the past 10 years exceeds the storage capacity across all media types. While the storage systems play a critical role in modern memory hierarchy, their interfaces and simulation models are overly simplified by computer-system architecture research. Specifically, gem5, a popular full system simulator, includes only Integrated Drive Electronics interface, which was originally designed three decades ago, and simulates the underlying storage device with a constant latency value. In this work, we implement an NVMe disk and controller to enable a realistic storage stack of next generation interfaces and integrate them into gem5 and a high-fidelity solid state disk simulation model. We verify the functionalities of NVMe that we implemented, using a standard user-level tool, called NVMe command line interface. Our evaluation results reveal that the performance of a high performance SSD can significantly vary based on different software stacks and storage controllers even under the same condition of device configurations and degrees of parallelism. Specifically, the traditional interface caps the performance of the SSD by 95%, whereas NVMe interface we implement in gem5 can successfully reveal the true performance aggregated by many underlying flash-based media.

ForenVisor: A Tool for Acquiring and Preserving Reliable Data in Cloud Live Forensics

Live forensics is an important technique in cloud security but is facing the challenge of reliability. Most of the live forensic tools in cloud computing run either in the target Operating System (OS), or as an extra hypervisor. The tools in the target OS are not reliable, since they might be deceived by the compromised OS. Furthermore, traditional general purpose hypervisors are vulnerable due to their huge code size. However, some modules of a general purpose hypervisor, such as device drivers, are indeed unnecessary for forensics. In this paper, we propose a special purpose hypervisor, called ForenVisor, which is dedicated to reliable live forensics. The reliability is improved in three ways: reducing Trusted Computing Base (TCB) size by leveraging a lightweight architecture, collecting evidence directly from the hardware, and protecting the evidence and other sensitive files with Filesafe module. We have implemented a proof-of-concept prototype on the Windows platform, which can acquire the process data, raw memory, and I/O data, such as keystrokes and network traffic. Furthermore, we evaluate ForenVisor in terms of code size, functionality, and performance. The experiment results show that ForenVisor has a relatively small TCB size of about 13 KLOC, and only causes less than 10 percent performance reduction to the target system. In particular, our experiments verify that ForenVisor can guarantee that the protected files remain untampered, even when the guest OS is compromised by viruses, such as `ILOVEYOU' and Worm.WhBoy. Also, our system can be loaded as a hypervisor without needing to pause the target OS. This allows it to not only avoid destructing but also to gather the live evidence of the target OS. We also posted the source code of ForenVisor on Github.

Automated and reliable resource release in device drivers based on dynamic analysis

In a modern operating system, device drivers acquire system resources to work. The acquired resources should be explicitly released by the drivers, because the operating system never reclaims them. Moreover, improper resource release can cause system crashes or hangs. Thus resource release is very important to driver reliability. However, according to our study on Linux driver mailing lists, many applied patches involve the modifications of resource release. Thus current resource management in drivers is not reliable enough.In this paper, we propose a novel approach named AutoRR, which can automatically and reliably release resources based on dynamic analysis. To identify resource handling operations, we use the dynamic specification-mining technique to mine resource acquiring and releasing functions. During execution, we maintain a resource-state list by intercepting the mined functions. If the driver fails to release acquired resources, AutoRR will report bugs and call corresponding releasing functions to safely release the resources. Dynamic analyses of resource dependency, allocation hierarchy, error handling form and releasing time are performed to avoid introducing new bugs when releasing resources. The evaluation on 12 Linux drivers shows that 40 detected bugs are all successfully and safely tolerated, and the overhead is only 7.84%.

Real-Time GPU Resource Management with Loadable Kernel Modules

Graphics processing unit (GPU) programming environments have matured for general-purpose computing on GPUs. Significant challenges for GPUs include system software support for bounded response times and guaranteed throughput. In recent years, GPU technologies have been applied to real-time systems by extending the operating system modules to support real-time GPU resource management. Unfortunately, such a system extension makes it difficult to maintain the system with version updates because the OS kernel and device drivers must be modified at the source-code level, thereby preventing continuous research and development of GPU technologies for real-time systems. A loadable kernel module (LKM) framework, called Linux Real-Time eXtention with GPUs (Linux-RTXG), for managing real-time GPU resources with Linux without modifying the OS kernel and device drivers is proposed and evaluated experimentally. Linux-RTXG provides mechanisms for interrupt interception and independent synchronization to achieve real-time scheduling and resource reservation capabilities for GPU applications on top of existing device drivers and runtime libraries. Experimental results demonstrate that the overhead incurred by introducing the proposed Linux-RTXG is comparable to that of introducing existing kernel-dependent approaches. In addition, the results demonstrate that multiple GPU applications can be scheduled successfully by Linux-RTXG to meet their priority and quality-of-service requirements in real time.

Wireless Interface Bonding Supporting In-Order Delivery and Automatic Load Balancing

Wireless interface bonding is an important technique in multiradio systems, where multiple radios can be combined to establish a fast link between nodes. However, existing interface bonding modules are not well-suited for wireless interfaces due to lack of functionalities to cope with varying channel capacity. Variance in throughput and delay of the individual radios can cause significant degradation of transmission control protocol throughput due to suboptimal scheduling and out-of-order delivery. Since condition of wireless channels is dynamic, capacity of each channel cannot be predicted offline which makes the packet scheduling challenging. Naive queue management for in-order delivery could also be hazardous to the throughput due to long dwell time of packets at the receiver queue. This paper presents an extension to Linux bonding driver called the new load balancing (NLB) mode, which is designed to combine multiple WLAN interfaces into a single virtual interface. The NLB mode supports automatic load balancing and in-order delivery, and together, they make a multichannel link that behaves like a single link with aggregated bandwidth. Automatic load balancing is done using receiver measurements on interarrival time of consecutive packets. In-order delivery is implemented using a receive queue and a fast loss detection scheme which prevents long dwell time of packets at the queue. The NLB mode does not require modifications to physical network device drivers which makes it usable with devices from any vendor. Performance evaluations using OpenWrt-based wireless devices show that the NLB mode can efficiently aggregate bandwidths of channels under various conditions.

EPICS device support for an ATCA CDAQ Board with hot-plug capabilities

The Advanced Telecommunications Computing Architecture (ATCA) standard defines a high performance technical solution that meets the requirements for fast controllers on large-scale physics experiments like ITER. This platform provides high throughput, scalability and features for high availability such as redundancy and intelligent platform management which are essential for steady state experiments.An ATCA Control and Data Acquisition (CDAQ) demonstration system was developed for the ITER Fast Plant System Controller (FPSC) project, which is already available in the ITER Catalog. This system comprises a board with 48 galvanic isolated analog and/or digital channels configurable as input or output with digital signal processing capabilities performed by a Field Programmable Gate Array (FPGA) and an ATCA carrier.The Experimental Physics and Industrial Control System (EPICS) is a set of open source software tools, libraries and applications used worldwide to create distributed soft real-time control systems for scientific instruments. To provide the hardware integration on the EPICS environment, a device support has been developed as a software layer, which is comparable to the abstraction layer provided by the device driver on the Operating Systems.This paper presents the implementation and test of an EPICS Device Support for the ATCA CDAQ Board that comprises templates for easy configuration of the entire system. This solution also allows simultaneous and independent acquisition by each board, providing hot-plug features which support insertion and removal of boards while keeping other modules and the overall system running.Operation with several boards and different versions of Linux operating system was performed and the results are presented.

Research of Building the Monitoring System of Cleaning in Place Applying MCGS

Cleaning In-place (CIP) system is a set of technical systems including cleaning main unit and software technology. The paper is introduced with the technical scheme of real-time process monitoring system using for CIP; designed by the hardware configuration of signal acquisition, signal transformation and data control in monitoring system; used MCGS to realize with the monitoring and controlling configuration design of central computer, real-time database build and peripheral device driver, monitoring parameters scale transforming, data acquisition module design, and cleaning process control program design, then ,the man-machine interface is achieved, real-time process animation is displayed, automatic and real-time monitoring the CIP process, real-time data browsing and preservation, as well as real-time and historical data trend is displayed and report output functions.

A Lightweight OS-Level Virtualization Architecture Based on Android

All kinds of intelligent terminal equipment emerge in endlessly and grow explosively. Typical devices, such as smartphones and tablets, are becoming more and more popular, furthermore, intelligent equipment market share has more than that on PCs. And on mobile devices area, the demand for virtualization technology is gradually increasing. As an important branch of computer technology development, operating system level virtualization is becoming a hot spot of current research due to its low overhead and the advantages of lightweight. In this paper, based on the Android system on mobile devices, implement a prototype which can run multiple virtual system instances on only an Android OS by modifying the namespace mechanism in the Linux kernel to and expand into driver namespace mechanism. In addition, put forward a model called the active- inactive model guaranteeing the process if and only if in the active namespace to operate the device drivers, which was designed and implemented a new scheme of operating system level virtualization.

Verifying Increasingly Expressive Temporal Logics for Infinite-State Systems

Temporal logic is a formal system for specifying and reasoning about propositions qualified in terms of time. It offers a unified approach to program verification as it applies to both sequential and parallel programs and provides a uniform framework for describing a system at any level of abstraction. Thus, a number of automated systems have been proposed to exclusively reason about either Computation-Tree Logic (CTL) or Linear Temporal Logic (LTL) in the infinite-state setting. Unfortunately, these logics have significantly reduced expressiveness as they restrict the interplay between temporal operators and path quantifiers, thus disallowing the expression of many practical properties, for example, “along some future an event occurs infinitely often.” Contrarily, CTL * , a superset of both CTL and LTL, can facilitate the interplay between path-based and state-based reasoning. CTL * thus exclusively allows for the expressiveness of properties involving existential system stabilization and “possibility” properties. Until now, there have not existed automated systems that allow for the verification of such expressive CTL * properties over infinite-state systems. This article proposes a method capable of such a task, thus introducing the first known fully automated tool for symbolically proving CTL * properties of (infinite-state) integer programs. The method uses an internal encoding that admits reasoning about the subtle interplay between the nesting of temporal operators and path quantifiers that occurs within CTL * proofs. A program transformation is first employed that trades nondeterminism in the transition relation for nondeterminism explicit in variables predicting future outcomes when necessary. We then synthesize and quantify preconditions over the transformed program that represent program states that satisfy a CTL * formula. This article demonstrates the viability of our approach in practice, thus leading to a new class of fully-automated tools capable of proving crucial properties that no tool could previously prove. Additionally, we consider the linear-past extension to CTL * for infinite-state systems in which the past is linear and each moment in time has a unique past. We discuss the practice of this extension and how it is further supported through the use of history variables. We have implemented our approach and report our benchmarks carried out on case studies ranging from smaller programs to demonstrate the expressiveness of CTL * specifications, to larger code bases drawn from device drivers and various industrial examples.

Simulation Technology of Configurable Airborne Electromechanical Equipment Based on QEMU

Airborne electromechanical systems have the characteristics of high complexity, reliability and costs, therefore a lot of simulation is needed. In order to make software developers simulate a variety of devices and conduct semi-physical simulation or digital simulation under the same framework. In this paper, the virtual simulation technology is used to achieve the configurable simulation of airborne electromechanical devices, and simulation devices are used to build a simulation platform. In QEMU virtual machine the simulation of equipment front-end interface is realized in order to use real device driver, a thread is used to simulate the device function, finally, the data is transferred to data transmission module to simulate multiple data exchange methods of equipment. In the device function simulation module dynamic loading technology is used. Using C and Lua hybrid programming method to realize the equipment function of flexible and configurable. The experimental results show that only need to modify the configuration script the different simulation of airborne electromechanical equipment can be achieved.

GPU-based low-level trigger system for the standalone reconstruction of the ring-shaped hit patterns in the RICH Cherenkov detector of NA62 experiment

This project aims to exploit the parallel computing power of a commercial Graphics Processing Unit (GPU) to implement fast pattern matching in the Ring Imaging Cherenkov (RICH) detector for the level 0 (L0) trigger of the NA62 experiment. In this approach, the ring-fitting algorithm is seedless, being fed with raw RICH data, with no previous information on the ring position from other detectors. Moreover, since the L0 trigger is provided with a more elaborated information than a simple multiplicity number, it results in a higher selection power. Two methods have been studied in order to reduce the data transfer latency from the readout boards of the detector to the GPU, i.e., the use of a dedicated NIC device driver with very low latency and a direct data transfer protocol from a custom FPGA-based NIC to the GPU. The performance of the system, developed through the FPGA approach, for multi-ring Cherenkov online reconstruction obtained during the NA62 physics runs is presented.

A low-latency storage stack for fast storage devices

Modern storage systems are facing an important challenge of making the best use of fast storage devices. Even though the underlying storage devices are being enhanced, the traditional storage stack falls short of utilizing the enhanced characteristics, as it has been optimized specifically for hard disk drives. In this article, we optimize the storage stack to maximize the benefit of low latency that fast storage devices provide. Our approach is to simplify the I/O path from application to the fast storage device by removing inefficient layers and the conventional block I/O. The proposed stack consists of three layers: an optimized device driver, a low-latency file system called L2FS, and a simplified VFS. The device driver provides a simple file I/O API to the file system instead of the existing block I/O API. L2FS, a variant of EXT4, performs low-latency I/O operations by using the file I/O API that our optimized device driver provides. We implement our storage stack on Linux 3.14.3 and evaluate it with multiple benchmarks. The results show that our system improves the throughput by up to 6.6 times and reduces the latency by an average of 54% compared to the existing storage stack on fast storage.

A Dual-Mode Driver IC With Monolithic Negative Drive-Voltage Capability and Digital Current-Mode Controller for Depletion-Mode GaN HEMT

This work presents a driver and controller integrated circuit (IC) for depletion-mode gallium nitride (GaN) high-electron-mobility transistors (HEMTs). The dual-mode driver can be configured for cascode-drive (CD) or HEMT-drive (HD) mode. In the CD mode, a cascode low-voltage DMOS is driven to achieve high-speed normally OFF operation. An active clamping circuit is proposed for the DMOS breakdown protection. In the HD mode, an HEMT gate driver with negative drive-voltage capability and programmable slope control is presented. A digital peak current-mode controller is also integrated with the dual-mode driver. The IC was implemented in a 140-nm automotive bipolar-CMOS-DMOS silicon-on-insulator process. The driver/controller IC is copackaged with an optimized 600-V GaN HEMT fabricated in a GaN-on-Si process. The solution was verified to operate at up to 1 MHz in a 35-W boost converter prototype and achieves a programmable switching-node $dv/dt$ of up to 20 V/ns. To the best of the author's knowledge, this is the first monolithic integration of a cascode MOSFET, device driver, and digital current-mode controller that is designed specifically for high-voltage GaN devices.

Fast polyhedra abstract domain

Numerical abstract domains are an important ingredient of modern static analyzers used for verifying critical program properties (e.g., absence of buffer overflow or memory safety). Among the many numerical domains introduced over the years, Polyhedra is the most expressive one, but also the most expensive: it has worst-case exponential space and time complexity. As a consequence, static analysis with the Polyhedra domain is thought to be impractical when applied to large scale, real world programs. In this paper, we present a new approach and a complete implementation for speeding up Polyhedra domain analysis. Our approach does not lose precision, and for many practical cases, is orders of magnitude faster than state-of-the-art solutions. The key insight underlying our work is that polyhedra arising during analysis can usually be kept decomposed, thus considerably reducing the overall complexity. We first present the theory underlying our approach, which identifies the interaction between partitions of variables and domain operators. Based on the theory we develop new algorithms for these operators that work with decomposed polyhedra. We implemented these algorithms using the same interface as existing libraries, thus enabling static analyzers to use our implementation with little effort. In our evaluation, we analyze large benchmarks from the popular software verification competition, including Linux device drivers with over 50K lines of code. Our experimental results demonstrate massive gains in both space and time: we show end-to-end speedups of two to five orders of magnitude compared to state-of-the-art Polyhedra implementations as well as significant memory gains, on all larger benchmarks. In fact, in many cases our analysis terminates in seconds where prior code runs out of memory or times out after 4 hours. We believe this work is an important step in making the Polyhedra abstract domain both feasible and practically usable for handling large, real-world programs.

CSI Phase Fingerprinting for Indoor Localization With a Deep Learning Approach

With the increasing demand of location-based services, indoor localization based on fingerprinting has become an increasingly important technique due to its high accuracy and low hardware requirement. In this paper, we propose PhaseFi, a fingerprinting system for indoor localization with calibrated channel state information (CSI) phase information. In PhaseFi, the raw phase information is first extracted from the multiple antennas and multiple subcarriers of the IEEE 802.11n network interface card by accessing the modified device driver. Then a linear transformation is applied to extract the calibrated phase information, which we prove to have a bounded variance. For the offline stage, we design a deep network with three hidden layers to train the calibrated phase data, and employ the weights of the deep network to represent fingerprints. A greedy learning algorithm is incorporated to train the weights layer-by-layer to reduce computational complexity, where a subnetwork between two consecutive layers forms a restricted Boltzmann machine. In the online stage, we use a probabilistic method based on the radial basis function for online location estimation. The proposed PhaseFi scheme is implemented and validated with extensive experiments in two representation indoor environments. It is shown to outperform three benchmark schemes based on CSI or received signal strength in both scenarios.

안드로이드 장치 드라이버에 대한 효과적 취약점 탐지 기법

안드로이드 및 리눅스 기반 임베디드 시스템에서는 디바이스 드라이버가 커널 함수로 포함되는 구조로 되어 있다. 어떤 디바이스 드라이버들의 경우, 여러 Third-party에 의해 제공되는 소프트웨어(펌웨어)가 포함되는데, 그 보안 수준에 대해 검토되지 않고 사용되는 경우가 많다. 보안 취약점 분석을 위해 일반적으로 사용되는 정적 분석의 경우, 오탐 가능성으로 인하여 실제 권한상승과 같은 주요 취약점을 확인하는데 많은 비용이 발생한다. 본 논문에서는 안드로이드 시스템에서 사용되는 디바이스 드라이버를 대상으로 정적 및 동적 분석 기반의 효과적인 보안 취약점 탐지 기법을 제시하고 그 효용성을 확인한다.

Towards an efficient snapshot approach for virtual machines in clouds

High-availability of virtual machines is of significant importance for a cloud computing environment, because cloud services may be compromised due to the system maintenance, malicious attacks, and hardware and software failures. The virtual machine (VM) snapshot can effectively back up the state, disk data, and configuration of a machine at a specific time point. However, the existing VM snapshot methods suffer from performance issues such as long downtime and I/O performance degradation during a live snapshot. To address such issues, we proposed an efficient VM snapshot system, iROW (improved Redirect-on-Write), based on the qemu-kvm virtual block device driver. iROW employs the following techniques. (1) A bitmap-based light-weight index method is designed to reduce the query cost of the existing two-level index table structure compared with qcow2. (2) An index-free approach is used for VM state data to improve the performance of data saving and loading operations of VM state. (3) VM state data is separated from disk image data in a snapshot. (4) The free page detection (FPD) is designed using virtual machine introspection to identify and skip saving free pages in the guest OS during snapshotting, thus reducing the VM state snapshot creation time and the snapshot disk space usage. Our experimental results demonstrate that iROW is evidently advantageous over qcow2 in performance, in terms of the disk snapshot, the state snapshot and the disk I/O.

Static analysis by abstract interpretation of functional properties of device drivers in TinyOS

In this paper, we present a static analysis by Abstract Interpretation of device drivers developed in the TinyOS operating system, which is considered as the de facto system in wireless sensor networks. We focus on verifying user-defined functional properties describing safety rules that programs should obey in order to interact correctly with the hardware. Our analysis is sound by construction and can prove that all possible execution paths follow the correct interaction patterns specified by the functional property. The soundness of the analysis is justified with respect to a preemptive execution model where interrupts can occur during execution depending on the configuration of specific hardware registers. The proposed solution performs a modular analysis that analyzes every interrupt independently and aggregates their results to over-approximate the effect of preemption. By doing so, we avoid reanalyzing interrupts in every context where they are enabled which improves considerably the scalability of the solution. A number of partitioning techniques are also presented in order to track precisely some crucial information, such as the hardware state and the tasks queue. We have performed several experiments on real-world TinyOS device drivers of the ATmega128 MCU and promising results demonstrate the effectiveness of our analysis.

Toward compositional verification of interruptible OS kernels and device drivers

An operating system (OS) kernel forms the lowest level of any system software stack. The correctness of the OS kernel is the basis for the correctness of the entire system. Recent efforts have demonstrated the feasibility of building formally verified general-purpose kernels, but it is unclear how to extend their work to verify the functional correctness of device drivers, due to the non-local effects of interrupts. In this paper, we present a novel compositional framework for building certified interruptible OS kernels with device drivers. We provide a general device model that can be instantiated with various hardware devices, and a realistic formal model of interrupts, which can be used to reason about interruptible code. We have realized this framework in the Coq proof assistant. To demonstrate the effectiveness of our new approach, we have successfully extended an existing verified non-interruptible kernel with our framework and turned it into an interruptible kernel with verified device drivers. To the best of our knowledge, this is the first verified interruptible operating system with device drivers.