Device Characteristics Of MOSFETs Research Articles

Research on the Switching Characteristics Based on the SiC MOSFET Model

With the continuous development of power electronics technology, the third-generation semiconductor materials represented by SiC and GaN have significant advantages in the band gap width, breakdown electric field, thermal conductivity, electron saturation rate and other key parameters, which meet the needs of modern industry for high power, high voltage and high frequency. When the SiC MOSFET plays its high frequency advantage, with the increase of switching frequency, the voltage change rate and current change rate of the device will be larger in the process of turning on and off. This paper mainly analyzes the characteristics of SiC MOSFET devices, and modifies the model based on the model provided by the manufacturer. By establishing static and dynamic test circuits, the static characteristic curves of the model were observed, and the drain voltage and current waveforms of the original model and the optimized model were compared during the switching process. The results show that the switching time of the optimized model is improved, and the oscillation waveform is greatly improved. Then, the accuracy of the optimized model is verified by the double-pulse circuit, and the drain source voltage and the drain source current are studied and observed under different temperature and drive resistance conditions. This paper provides data support for improving the switching characteristics of SiC MOSFET in practical applications.

Characterization of As2Se3/MoO3 heterojunction designed for multifunctional operations

In this article, As2Se3/MoO3 heterojunction devices are structurally, compositionally, optically and electrically characterized. The heterojunction devices which are prepared by the thermal evaporation technique under vacuum pressure of 10–5 mbar are observed to exhibit amorphous nature of growth. The optical spectrophotometry measurements and analyses on the heterojunction devices revealed a conduction and valence band offsets of values of 2.64 and 4.08 eV, respectively. In addition, the dielectric dispersion and the optical conductivity parametric analyses have shown that the heterojunction could exhibit large drift mobility value up to 73.7 cm2 V−1 s−1. From electrical point of view, while the capacitance- voltage curves reveal characteristics of MOSFET devices, the current--voltage curves display tunneling diode characteristics. The features of the As2Se3/MoO3 devices including the band offsets, drift mobility, plasmon frequency, microwave band filtering and MOSFET characteristics make them attractive for use as thin films transistors suitable electrical and optical applications.

Characterization and Modeling of 0.18μm Bulk CMOS Technology at Sub-Kelvin Temperature

Previous cryogenic electronics studies are mostly at 77K and 4.2K. Cryogenic characterization of a 0.18μm standard bulk CMOS technology (operating voltages: 1.8V and 5V) is presented in this paper. Several NMOS and PMOS devices with different width to length ratios (W/L) were extensively tested and characterized under various bias conditions at sub-kelvin temperature. In addition to devices dc characteristics, the kink effect and current overshoot phenomenon are observed and discussed at sub-kelvin temperature. Especially, the current overshoot phenomenon in PMOS devices at sub-kelvin temperature is shown for the first time. The transfer characteristics of MOSFET devices (1.8V W/L = 10μm/10μm) at sub-kelvin temperature are modeled using the simplified EKV model. This work facilitates the CMOS circuits design and the integration of CMOS circuits with silicon-based quantum chips at extremely low temperatures.

DC Modeling and Geometry Scaling of SiC Low-Voltage MOSFETs for Integrated Circuit Design

This paper presents the SPICE model development of the static characteristics of silicon carbide (SiC) lateral n-channel and p-channel MOSFETs based on the widely used BSIM4 compact model. The methodology for length and width scaling of the MOSFETs is demonstrated. The transfer ( $I_{\text{D}}$ – $V_{\text{G}}$ ) and output ( $I_{\text{D}}$ – $V_{\text{D}}$ ) characteristics of the SiC low-voltage MOSFETs are significantly different from their Si counterparts mainly due to the presence of the interface trapped charge, and proper modifications of the dc equations are required to accurately model the characteristics. The relatively poorer quality of the oxide-semiconductor interface in a SiC MOSFET compared to Si gives rise to valid energy states inside the bandgap. The trapped charges in these interface states are responsible for mobility degradation, higher subthreshold slope (SS), soft saturation, increase in the flat band and threshold voltage, and exaggerated body effects. In this paper, the effects of the interface trapped charge on the static characteristics of the SiC MOSFETs are intensively studied and accurate compact models are developed and incorporated in the core BSIM4 dc current equations to accurately model the SiC MOSFET ${I}$ – ${V}$ behavior. A new parameter extraction sequence is also proposed to optimize the model and the simulated characteristics are matched with the measured characteristics of SiC MOSFET devices.

(Keynote) Nitrogen-Ion Implantation Doping of Ga2O3 and Its Application to Transistors

As a key ultra-wide bandgap semiconductor, gallium oxide (Ga2O3) has been attracting much interest for power device applications due to its excellent material properties based on an extremely large bandgap of 4.5 eV and the availability of high-quality, large-diameter wafers produced from bulk single crystals synthesized by melt growth methods. Despite having received only little attention, the ease of both n- and p-type ion implantation doping is another very attractive and important feature for Ga2O3 device technologies. Recently, we succeeded in developing nitrogen (N)-ion implantation doping technology to form p-type Ga2O3 [1]. Note that it is almost impossible to obtain p-type Ga2O3 with effective hole conductivity as for conventional semiconductors. This is not only due to a lack of shallow acceptors with moderate activation energies but also because the valence band structure of Ga2O3, which is composed of O 2p orbitals, is characterized by a very large hole effective mass and conduces to self-trapping of holes with associated characteristic lattice distortions. Therefore, p-Ga2O3 is only useful for engineering large energy barriers in the form of p-n junctions. We have experimentally confirmed that a N-ion implanted p-Ga2O3 region formed in n-Ga2O3 can be utilized as a current blocking layer. In this talk, we first discuss the material properties of p-Ga2O3 formed by N-ion implantation doping. Then, the device process and characteristics of vertical normally-on Ga2O3 MOSFETs fabricated by using multiple Si- and N-ion implantations are presented [2]. This work was partially supported by Council for Science, Technology and Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), “Next-generation power electronics” (funding agency: New Energy and Industrial Technology Development Organization). [1] M. H. Wong, C.-H. Lin, A. Kuramata, S. Yamakoshi, H. Murakami, Y. Kumagai, and M. Higashiwaki, Appl. Phys. Lett. 113, 102103 (2018). [2] M. H. Wong, K. Goto, H. Murakami, Y. Kumagai, and M. Higashiwaki, IEEE Electron Device Lett. 40, 431 (2019).

Reliability of SiC Power Devices against Cosmic Ray Neutron Single-Event Burnout

High-energy neutrons produced by cosmic ray interactions with our atmosphere are known to cause single-event burnout (SEB) failure in power devices operating at high fields. We have performed accelerated high-energy neutron SEB testing of SiC and Si power devices at the Los Alamos Neutron Science Center (LANCSE). Comparing Wolfspeed SiC MOSFETs having different voltage (900V – 3300V) and current (3.5A – 72A) ratings, we find a universal behavior when scaling failure rates by active area, and scaling drain bias by avalanche voltage. Moreover, diodes and MOSFETs behave similarly, revealing that the SiC drift dominates the failure characteristics for both device types. This universal scaling holds for SiC MOSFETs from other manufacturers as well. The SEB characteristics of Si power IGBT and MOSFET devices show that near their rated voltages failure rates of Si devices can be 10X higher than that of comparable SiC MOSFET devices. Thus, Si devices are more susceptible to SEB failure from voltage overshoot conditions.

Real-time and on-site γ-ray radiation response testing system for semiconductor devices and its applications

The construction of a turnkey real-time and on-site radiation response testing system for semiconductor devices is reported. Components of an on-site radiation response probe station, which contains a 1.11GBq Cs137 gamma (γ)-ray source, and equipment of a real-time measurement system are described in detail for the construction of the whole system. The real-time measurement system includes a conventional capacitance–voltage (C–V) and stress module, a pulse C–V and stress module, a conventional current–voltage (I–V) and stress module, a pulse I–V and stress module, a DC on-the-fly (OTF) module and a pulse OTF module. Electrical characteristics of MOS capacitors or MOSFET devices are measured by each module integrated in the probe station under continuous γ-ray exposure and the measurement results are presented. The dose rates of different gate dielectrics are calculated by a novel calculation model based on the Cs137 γ-ray source placed in the probe station. For the sake of operators’ safety, an equivalent dose rate of 70nSv/h at a given operation distance is indicated by a dose attenuation model in the experimental environment. HfO2 thin films formed by atomic layer deposition are employed to investigate the radiation response of the high-κ material by using the conventional C–V and pulse C–V modules. The irradiation exposure of the sample is carried out with a dose rate of 0.175rad/s and ±1V bias in the radiation response testing system. Analysis of flat-band voltage shifts (ΔVFB) of the MOS capacitors suggests that the on-site and real-time/pulse measurements detect more serious degradation of the HfO2 thin films compared with the off-site irradiation and conventional measurement techniques.

Energy gap tunable graphene antidot nanoribbon MOSFET: A uniform multiscale analysis from band structure to transport properties

A detailed simulation study of the graphene antidot nanoribbon (GANR) and its corresponding MOSFET characteristics is shown in this paper. The research uncovers that the GANR's energy gap (Eg) is continuously tunable by its topography parameters, such as the ribbon's width, the antidot density and the antidot size. At the same ribbon width, the Eg of GANR can be tuned flexibly, while it is only a fixed value in GNR. Owing to these flexible Eg regulations, device applications based on GANRs could be more widely used. Furthermore, brief compact descriptions are extracted between GANR's band gap and MOSFET's device characteristics. Using Eg as a bridge, the relations between the structure characteristics and transport properties of GANR MOSFETs are constructed directly. The results reveal that the antidot nanoribbon structure is a good candidate for MOSFET applications. In the calculation, an elaborate ab initio-based study framework from band structure to device performance is adopted. Using the maximally localized Wannier functions (MLWF) method, the impacts on band structures, which are induced by crystal optimizations, are reserved into the TB Hamiltonian without any parameter revisions. This method overcomes the gap between nano-scale carbon structures' material characteristics and their device applications.

Mixed Tunnel-FET/MOSFET Level Shifters: A New Proposal to Extend the Tunnel-FET Application Domain

In this paper, we identify the level shifter (LS) for voltage up-conversion from the ultralow-voltage regime as a key application domain of tunnel FETs (TFETs). We propose a mixed TFET–MOSFET LS design methodology, which exploits the complementary characteristics of TFET and MOSFET devices. Simulation results show that the hybrid LS exhibits superior dynamic performance at the same static power consumption compared with the conventional MOSFET and pure TFET solutions. The advantage of the mixed design with respect to the conventional MOSFET approach is emphasized when lower voltage signals have to be up-converted, reaching an improvement of the energy-delay product up to three decades. When compared with the full MOSFET design, the mixed TFET–MOSFET solution appears to be less sensitive toward threshold voltage variations in terms of dynamic figures of merit, at the expense of higher leakage variability. Similar results are obtained for four different LS topologies, thus indicating that the hybrid TFET–MOSFET approach offers intrinsic advantages in the design of LS for voltage up-conversion from the ultralow-voltage regime compared with the conventional MOSFET and pure TFET solutions.

Modified Interface State Charge Model for 4H-SiC Power MOSFETs

We propose a modified model for interface-state charges to comprehend the device characteristics of 4H-SiC MOSFETs. Device characteristics, such as channel current and channel capacitance, and their dependence on temperature were intuitionally expected by regarding interface-state charges at the conduction band edge as stagnation. We also found that the observed mobility was underestimated through conventional experimental methods compared with actual channel mobility due to stagnant carriers.

Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices

This paper investigates the feasibility of sub-0.2 V high-speed low-power circuits with hetero-channel MOSFET and emerging Tunneling FET (TFET) devices. First, the device designs and characteristics of hetero-channel MOSFET and TFET devices are discussed and compared. Due to the significant leakage current of ultra-low VT hetero-channel MOSFET devices, assist-circuits are required for hetero-channel MOSFET-based circuits to operate at 0.2 V. Second, the delay, dynamic energy and the Standby power of hetero-channel TFET-based and MOSFET-based logic circuits including Inverter, NAND, BUS Driver, and Latch are analyzed and evaluated. The results indicate that hetero-channel TFET-based circuits with Dual Oxide (DOX) device design to reduce the Miller capacitance provide the potential to achieve high-speed low-power operation at VDD=0.2 V, while the use of assist-circuits in MOSFET-based design improves the delay and dynamic energy at the expense of increased device count, circuit area, and large Standby and sleep-mode leakage power. Finally, the impacts of temperature and process variations on TFET-based and MOSFET-based logic circuits are discussed.

Enhanced High Temperature Performance of PD-SOI MOSFETs in Analog Circuits Using Reverse Body Biasing

Analog circuit realized in a PD-SOI (Partially-Depleted Silicon-on-Insulator) CMOS process for a wide temperature range up to 400 °C are significantly affected by the MOSFET device characteristics at high temperatures. As leakage currents increase with temperature, the analog device performance, e.g. intrinsic gain and bandwidth tend to decrease. Both effects influence the precision of analog circuits and lead to malfunction of the circuitry at high temperatures. Enhancement of the MOSFET device performance and improved design techniques are required to handle these issues. In this paper, we demonstrate that reverse body biasing (RBB) is a useful method to improve the analog performance of PD-SOI transistors and also to push the limit of analog circuit design in SOI technology beyond 300 °C. It allows beneficial FD (fully depleted) device characteristics in a 1.0 μm PD-SOI CMOS process by manipulating the depletion condition of the silicon film. Due to reduced leakage currents, operation in the moderate inversion region of the SOI transistor device up to 400 °C is feasible. The method is verified by experimental results of transistors with an H-shaped gate (HGATE), an analog switch, basic current mirrors, a two-stage operational amplifier and a bandgap voltage reference. The normalized leakage current of HGATE devices at high temperatures can be reduced by more than one order of magnitude. Thereby the gm/Id factor is improved significantly especially in the moderate inversion region, which has been inaccessible due to leakage currents. As a result, the intrinsic gain of HGATE transistors is improved. The method has also been applied to basic analog circuits. It has been found that RBB significantly reduces the errors related to leakage currents and enables the operation of analog circuits in PD-SOI technology up to 400 °C.

Effects of High-Energy Ion Irradiation on the Conduction Characteristics of HfO2-based MOSFET Devices

MOSFET devices with HfO2 gate oxides were irradiated with high-energy (120 MeV) Au ions. It was observed that the irradiation ca n cause both little or severe damage to the structures under test. We associate these effects with the soft and hard breakdown failure modes occurring in ultra-thin oxides. In both cases there is a large increment of the transistor off current. If the damage is not catastrophic a decrease of the transconductance and drain current characteristics can also be detected. This indicates that the transistor is still operational but with worst performance parameters.

Transfer of physically-based models from process to device simulations: Application to advanced SOI MOSFETs

Dopant implantation, followed by spike annealing is one of the main focus areas in the simulation of silicon processing due to its ability to form highly-activated ultra-shallow junctions. Coupled with the growing interest in the use of silicon-on-insulator (SOI) wafers, modelling and simulation of the influence of SOI structure on damage evolution and ultra-shallow junction formation on one hand, and on electrical MOSFET device characteristics on the other hand, are required. In this work, physically-based models of dopant implantation and diffusion, including amorphization, defect interactions and evolution, as well as dopant–defect interactions in both bulk silicon and SOI are integrated within a unique simulation tool to model the different physical mechanisms involved in the process of ultra-shallow junction formation. The application to 65 nm SOI MOSFET devices demonstrated the strong impact of the process simulation models on the simulated electrical device characteristics, in particular for both defect evolution and defect dopant interaction with the additional silicon/buried oxide (Si/BOX) interface. Simulation results of the threshold voltage ( V th) and the variation of the on- and off-state currents of the explored structures are in good agreement with experimental data and can provide important insight for optimizing the process in both bulk silicon and SOI technologies.

Nonvolatile memory characteristics of metallic nanodots as charge-storage nodes

The charge and discharge properties of NiSi nanodots in the gate oxide of MOS and MOSFET devices were investigated in order to utilize as the charge-storage nodes in a nonvolatile floating-gate memory. NiSi nanodots were formed by sputtering Ni and successive exposing to SiH 4 gas. The memory characteristics of MOS and MOSFET devices which contain the NiSi nanodots in the gate oxide were obtained through the capacitance–voltage measurements and the transient threshold voltage shift measurements. The window of threshold voltage shift was achieved to be 2.5 V when the gate bias voltages of ±20 V were applied for 1 s and 500 ms, respectively. The retention time of MOSFET memory-cell was estimated to be about 10 years.

Characterization, Modeling, and Application of 10-kV SiC MOSFET

Ten-kilovolt SiC MOSFETs are currently under development by a number of organizations in the United States, with the aim of enabling their applications in high-voltage high-frequency power conversions. The aim of this paper is to obtain the key device characteristics of SiC MOSFETs so that their realistic application prospect can be provided. In particular, the emphasis is on obtaining their losses in various operation conditions from the extensive characterization study and a proposed behavioral SPICE model. Using the validated MOSFET SPICE model, a 20-kHz 370-W dc/dc boost converter based on a 10-kV 4H-SiC DMOSFET and diodes is designed and experimentally demonstrated. In the steady state of the boost converter, the total power loss in the 15.45-mm2 SiC MOSFET is 23.6 W for the input power of 428 W. The characterization study of the experimental SiC MOSFET and the experiment of the SiC MOSFET-based boost converter indicate that the turn-on losses of SiC MOSFETs are the dominant factors in determining their maximum operation frequency in hard-switched circuits with conventional thermal management. Replacing a 10-kV SiC PiN diode with a 10-kV SiC JBS diode as a boost diode and using a small external gate resistor, the turn-on loss of the SiC MOSFET can be reduced, and the 10-kV 5-A SiC MOSFET-based boost converter is predicted to be capable of a 20-kHz operation with a 5-kV dc output voltage and a 1.25-kW output power by the PSpice simulation with the MOSFET model. The low losses and fast switching speed of 10-kV SiC MOSFETs shown in the characterization study and the preliminary demonstration of the boost converter make them attractive in high-frequency high-voltage power-conversion applications.

Device Modeling at Cryogenic Temperatures: Effects of Incomplete Ionization

We present a device performance modeling methodology that self-consistently resolves device operation at cryogenic temperatures (T > 30 K) in conjunction with incomplete ionization effects that take into account the change in dopant activation energies as a function of doping. Using this methodology, we developed a device simulator that predicts n-channel MOSFET (NMOSFET) device characteristics for a wide range of temperatures by solving semiconductor equations, along with the Poisson equation. Comparison of our calculated results with measurements shows that proper inclusion of variations in activation energy as a function of doping level is necessary for accurately monitoring device operation at cryogenic temperatures. Using dopant activation energies that are independent of doping levels leads to current rolloff and eventually device turn-off at low-temperature simulations. However, activation energy models that give lower activation energies for higher doping levels result in improved NMOSFET performance at colder temperatures, which agrees with experiments. Furthermore, calculations indicate that different incomplete ionization models affect the NMOSFET characteristics mainly through changes in the resistances of the heavily doped source and drain regions, and the substrate.

PSpice for Circuit Theory and Electronic Devices

PSpice for Circuit Theory and Electronic Devices is one of a series of five PSpice books and introduces the latest Cadence Orcad PSpice version 10.5 by simulating a range of DC and AC exercises. It is aimed primarily at those wishing to get up to speed with this version but will be of use to high school students, undergraduate students, and of course, lecturers. Circuit theorems are applied to a range of circuits and the calculations by hand after analysis are then compared to the simulated results. The Laplace transform and the s-plane are used to analyze CR and LR circuits where transient signals are involved. Here, the Probe output graphs demonstrate what a great learning tool PSpice is by providing the reader with a visual verification of any theoretical calculations. Series and parallel-tuned resonant circuits are investigated where the difficult concepts of dynamic impedance and selectivity are best understood by sweeping different circuit parameters through a range of values. Obtaining semiconductor device characteristics as a laboratory exercise has fallen out of favour of late, but nevertheless, is still a useful exercise for understanding or modelling semiconductor devices. Inverting and non-inverting operational amplifiers characteristics such as gain-bandwidth are investigated and we will see the dependency of bandwidth on the gain using the performance analysis facility. Power amplifiers are examined where PSpice/Probe demonstrates very nicely the problems of cross-over distortion and other problems associated with power transistors. We examine power supplies and the problems of regulation, ground bounce, and power factor correction. Lastly, we look at MOSFET device characteristics and show how these devices are used to form basic CMOS logic gates such as NAND and NOR gates.

Bendability of single-crystal Si MOSFETs investigated on flexible substrate

This letter reports on a device layer transfer (based on thermal bonding and grinding backside Si) process and device characteristics of Si MOSFETs on a flexible substrate, focusing mainly on the mechanical bendability of the device and resistance to fatigue. The results demonstrated a well-optimized bonding process, as indicated by the nearly indiscernible performance difference (e.g., subthreshold slope, V/sub th/, and I/sub dsat/) before and after the bonding of Si with the flexible substrate. The device characteristics indicate excellent bendability of Si MOSFETs on flexible substrate (e.g., for radius tested down to /spl plusmn/72 mm) and good immunity to fatigue (e.g., negligible performance drift tested up to /spl sim/10/sup 3/ bending cycles with a radius of /spl plusmn/126 mm). Results suggest the feasibility of this approach in achieving high-performance MOSFETs for applications in performance-sensitive and flexible electronics.

Temperature Effects of n-MOSFET Devices with Uniaxial Mechanical Strains

2This study proposes a method for the investigation of the effects of uniaxial stresses, in a temperature-dependent manner, to MOSFET device characteristics, such as mobility, threshold voltage, and on-current. This simple scheme did not require complicated instruments and generated more homogeneous stresses for elucidating the effects of uniaxial mechanical strains on MOSFET devices. Experimental and Results The NMOS transistors were fabricated on industry standard 12 in. Si wafers with a 001 surface and wafer notch on the 110 axis. The direction of the current flow for transistors with 45 orientation is along the 100 axis. Transmission electron micrographs TEMs of 40 nm gate length n-MOSFET are shown in Fig. 1b. The devices were patterned with 193 nm lithography. The standard processes of STI, gate oxide, SiN spacer, source/drain S/D implant, spike anneal, Ni salicide, and Cu interconnect processes were applied. During gate oxide formation, nitride treatment was added. At the end of the process flow, a highly tensile silicon nitride layer was deposited, which covered the source, drain, and gate stack. This capping layer created tensile stresses in the channel area. The gate oxynitride thickness was 1.2 nm and gate polysilicon thickness was 98.5 nm. The sidewall spacer was O/N/O structure. The unstrained devices without a nitride layer were also fabricated. The transport properties of electrons in unstrained and strained Si were studied along the crystallographic 100 directions in the linear regime. The mechanical stress was applied in parallel or perpendicular direction to the MOSFET current flow. We chose this coordinate system versus one aligned to 100 axes. Followed are descriptions of the proposed method Fig. 1. Square strips were cut from the wafer using the saw procedure. They were abraded from a thickness of 800 to 50 m and then placed on stainless steel foil, then pasted on an aluminum pedestal with a curvature of radius 2, 3, 4, and 5 mm, using adhesive tapes. The adhesive tape is heatproof below 573 K. The surface stress was determined using the relationship, 1 = t/2R and 2 = E * , where E is Young’s Modulus E = 130 GPa for 100 silicon orientation, t is the total thickness of the flakes, and R is the radius of the aluminum pedestal. The transfer characteristics of the devices were measured using a semiconductor parameter analyzer HP 4156C. This work studied the device characteristics at temperatures ranging from 303 to 363 K by imposing external mechanical longitudinal or transverse stress on a Si pedestal. Figure 2 shows the n-MOSFET mobility variations for unstrained device and the devices under tensile stresses or , where the subscript and refer to the directions parallel and transverse to the current flow in the plane of the n-MOSFETs. In Fig. 2a, the mobility under all three cases decreases as the temperature increases. Since a carrier moving through the crystal is scattered by a vibration of the lattice, we should expect the mobility to decrease as the sample is heated. 5 However, the percentage drops in