Development Of Semiconductor Technology Research Articles

A Method for Automatically Predicting the Radiation-Induced Vulnerability of Unit Integrated Circuits.

With the rapid development of semiconductor technology, the reduction in device operating voltage and threshold voltage has made integrated circuits more susceptible to the effects of particle radiation. Moreover, as process sizes decrease, the impact of charge sharing effects becomes increasingly severe, with soft errors caused by single event effects becoming one of the main causes of circuit failures. Therefore, the study of sensitivity evaluation methods for integrated circuits is of great significance for promoting the optimization of integrated circuit design, improving single event effect experimental methods, and enhancing the irradiation reliability of integrated circuits. In this paper, we first established a device model for the charge sharing effect and simulated it under reasonable conditions. Based on the simulation results, we then built a neural network model to predict the charge amounts in primary and secondary devices. We also propose a comprehensive automated method for calculating soft errors in unit circuits and validated it through TCAD simulations, achieving an error margin of 2.8-4.3%. This demonstrated the accuracy and effectiveness of the method we propose.

Computational Optical Scanning Holography

Holographic techniques are indispensable tools for modern optical engineering. Over the past two decades, research about incoherent digital holography has continued to attract attention. Optical scanning holography (OSH) can obtain incoherent holograms using single-pixel detection and structured illumination with Fresnel zone patterns (FZPs). Particularly by changing the size of a detector, OSH can also obtain holograms under coherently illuminated conditions. Since 1979, OSH has continuously evolved. According to the evolution of semiconductor technology, spatial light modulators (SLMs) come to be useful for various imaging fields. By using SLM techniques for OSH, the practicality of OSH is improved. These SLM-based OSH methods are termed computational OSH (COSH). In this review, the configurations, recording and reconstruction methods, and proposed applications of COSH are reviewed.

Fragile Foundations: Tracing Argentina's Semiconductor Saga amid Institutional Turmoil.

This article suggests that the persistent pattern of political and economic instability in Argentina has affected the development of semiconductor technology in Argentina, affecting secure resources, financial stability, and appropriate institutional frameworks. This article reconstructs Argentina's history of semiconductor technology to understand the initial research, development, and production of semiconductor technology and the emergence of the field of electronics knowledge in a peripheral country like Argentina. In-depth interviews with key players and analysis of institutional documents shed light on the achievements of the protagonists and their relationship to the country's political and economic context.

Low noise, analog electrocardiogram signal amplifier for wearable equipment

Due to the rapid development of semiconductor technology, the edges of electronic devices are getting smaller and the power consumption is getting lower and lower 3-op-amp instrumentation amplifier. However, there are still some problems such as excessive power consumption and noise. First, the disadvantages are identified, and then the shortcomings of the specialty are improved. So this design gives a low noise ECG equipment, which shows great performance in reducing noise to 3.94uV and the highest differential gain reaches 36.508376dB. It can be used in watches and other wearable devices for ECG signal detection. At the same time, this project can complete the required requirements and is suitable for some wearable devices. Its successful research could lead to more accurate ECG monitoring and consume less power in wearable devices. More importantly, its emergence brings new development ideas and development directions to ECG equipment, making ECG monitoring convenient and mobile.

Design and Implementation of DDS Signal Generator Based on FPGA

With the rapid development of semiconductor technology, the digital circuit of the control chip gradually replaces the analog circuit of the traditional signal generator, which improves the performance of the signal generator and reduces the cost of research, development and production. This paper proposes a design scheme that takes FPGA chip as the control center. The signal generator system mainly includes DAC module, FPGA module and key module. The system uses Verilog language to develop the sine wave digital signal generation and key switching frequency control logic circuit on FPGA. The frequency control word circuit in the FPGA module provides multiple frequency sine wave selection, and the look-up table circuit realizes the reading of different phases by controlling the read address of the ROM. The 14-bit high-speed DAC module converts the digital signals sent by FPGA into analog signals. The DAC module integrates low-pass filter processing to increase the smoothness of the signal. After testing, the system meets the design requirements.

Design of ECG circuits for wearable devices

Heart diseases have become more and more prominent in recent years. ECG signals can accurately reflect the health of hearts during the detection process. The use of wearable ECG devices requires low power consumption, a high common-mode rejection ratio, and minimal noise. Traditional research has concentrated on lowering the circuit's overall power dissipation, which typically results in less current flowing through the amplifier but higher circuit noise. Therefore, this places higher demands on the amplifier in the circuit. Electronic devices are becoming smaller due to the rapid development of semiconductor technology. Amplifiers designed for semiconductor devices can effectively solve the problems mentioned above. The circuit created in this study has a low power need, a high common-mode rejection ratio, is compact, has a high input impedance, and has a low input-referred noise level. In addition, LT-Spice software was used to design and simulate the circuit, and the results were analyzed and calculated accordingly. The circuit meets the requirements of the project design. The frequency range of the circuit is 1mHz - 227.9Hz. The differential gain of the circuit is 36.6dB. The integrated input-fred noise is 3.94uV. The total consumption of electricity is 4.67W. These data indicate that the circuit has a high gain in the frequency range of ECG signals, which can filter out other interference signals. It also solves the problems of power consumption and noise.

Research on heavy ion irradiation effects on SOI SRAM

SRAM based on SOI devices has been widely used in aerospace storage devices due to its good electrical characteristics and radiation resistance. However, with the development of semiconductor technology, the feature size of devices continues to shrink, and the irradiation effects of high-energy ions have become increasingly serious. Single event effect has become the biggest threat to the failure of the spacecraft. A mixed-simulation method was used to research the heavy ion irradiation effects on SOI SRAM. SRAM consists of two coupled inverters. Firstly, the voltage changes of the inverter and SRAM output nodes under heavy ion irradiation were compared and analyzed, then the influence of the device itself and heavy ion parameters on the single particle flipping effect of the SRAM is investigated, and finally the necessary conditions for the flipping of the stored information in the SRAM are discussed and derived. The results show that heavy ion incidence does not permanently change the final state of the inverter; devices in the off state in the SRAM will undergo information flipping only when they are irradiated by heavy ions, and the threshold voltage of the N-type MOSFET is lower than that of the P-type MOSFET; an increase in the penetration depth will accelerate the flipping speed of the SRAM, but when the LET is high, the influence of the penetration depth on the flipping speed decreases; the change of the stored information in the SRAM is the result of the combined effect of pulse width and pulse height.

Accurate Prediction and Reliable Parameter Optimization of Neural Network for Semiconductor Process Monitoring and Technology Development

Herein, novel neural network (NN) methods that improve prediction accuracy and reduce output variance of the optimized input in the gradient method for cross‐sectional data are proposed, and the variability evaluation approach of optimized inputs in the semiconductor process is suggested. Specifically, electrical parameter measurements (EPMs) and power‐delay product of industrial high‐k metal gate DRAM peripheral 29‐stage ring oscillator circuits, including NMOS, PMOS, and interconnects, are focused on. The proposed methods find an optimized input to achieve a lower NN output variance in the gradient descent than one multilayer perceptron (MLP) and mean ensemble of MLPs even when considering the variabilities of the devices and interconnects. The local optima problem of one MLP is resolved by utilizing multiple MLPs trained with different train/validation data, their trimmed mean, and an additional learnable layer. Moreover, adding the learnable layer secures versatility for various parametric datasets. The methods improve the prediction accuracy (R2) by 5.6–15.6% in sparse data space compared to one MLP and the mean ensemble, decrease the NN output variance of the optimized input by 73.0–81.6% compared to one MLP and the mean ensemble, and are successfully verified by implementing it on EPMs of 3977 test patterns of 314 wafers and 16 lots.

LARGE-SCALE SYNTHESIS OF HOMOGENEOUS WS2 FILMS BY PHYSICAL VAPOR DEPOSITION

TMDs are semiconductors, unlike graphene, and have a direct bandgap when converted from bulk to thin film. This property makes TMDs an ideal material for optoelectronic and photovoltaic applications due to their strong optical absorption and photoluminescence effect. The WS2, a popular TMD, has unique properties such as low friction coefficient, high thermal stability, and good electrical conductivity, and a bandgap energy of approximately 1.2 eV and 2.2 eV for indirect and direct behaviors. The article also discusses various methods for synthesizing WS2, including chemical vapor deposition (CVD), physical vapor deposition (PVD), hydrothermal synthesis, and solvothermal synthesis. PVD is a scalable method for producing large-area films and coatings with high quality, but the difficulty of controlling the sulfur or selenium sources in this method leads to the need for optimizing growth parameters for large-scale and high-quality WS2 film synthesis. The study reports the successful growth of large-scale and homogeneous WS2 films on a glass substrate using PVD and optimized substrate temperature. The results of this study provide valuable information for the advancement of WS2 film growth techniques and the development of WS2-based semiconductor technologies, such as transistors, diodes, photodetectors, and solar cells.

A Physics-Informed Automatic Neural Network Generation Framework for Emerging Device Modeling.

With the rapid development of semiconductor technology, traditional equation-based modeling faces challenges in accuracy and development time. To overcome these limitations, neural network (NN)-based modeling methods have been proposed. However, the NN-based compact model encounters two major issues. Firstly, it exhibits unphysical behaviors such as un-smoothness and non-monotonicity, which hinder its practical use. Secondly, finding an appropriate NN structure with high accuracy requires expertise and is time-consuming. In this paper, we propose an Automatic Physical-Informed Neural Network (AutoPINN) generation framework to solve these challenges. The framework consists of two parts: the Physics-Informed Neural Network (PINN) and the two-step Automatic Neural Network (AutoNN). The PINN is introduced to resolve unphysical issues by incorporating physical information. The AutoNN assists the PINN in automatically determining an optimal structure without human involvement. We evaluate the proposed AutoPINN framework on the gate-all-around transistor device. The results demonstrate that AutoPINN achieves an error of less than 0.05%. The generalization of our NN is promising, as validated by the test error and the loss landscape. The results demonstrate smoothness in high-order derivatives, and the monotonicity can be well-preserved. We believe that this work has the potential to accelerate the development and simulation process of emerging devices.

TCAD-Enabled Machine Learning—An Efficient Framework to Build Highly Accurate and Reliable Models for Semiconductor Technology Development and Fabrication

The requirements on data-driven Machine Learning models for industrial applications are often stricter, compared to those used for academic purposes, as model reliability is critical in industrial environments. Herein is introduced a framework which enables automated data generation with the goal of efficiently providing a data set sufficient to build a reliable and actionable model. Essential to this framework is the placement of the model training/testing data points, which need to be well distributed across the defined input parameter space. The framework is applied to semiconductor fabrication, wherein TCAD, a set of simulation tools that reproduce the physical processing and the final electrical performance of semiconductor devices, is a well-established capability. Transistor-level processing data is reproduced with TCAD simulations, from which the Machine Learning model is built. The framework described here assures that the resulting Machine Learning model fulfills the accuracy requirements across the parameter space. As an example application, the final Machine Learning model is then used to modify the process for a transistor, to obtain both better electrical performance and reduced variability.

Design and Implementation of an Automatic Test and Verification System for SoC

With the development of semiconductor technology in recent years, the design of SoC has become more and more complex. [1]In order to ensure the correctness of chip design and the success rate of chip taping out, the verification test of SoC becomes more and more important. This paper designs an automated test and verification system based on STM32 and analog switch matrix chips. The system has high reusability, good scalability, convenient maintenance and automated test, and can improve the efficiency of test and verification, reduce the cost and shorten the development cycle of SoC.

Quartz sand is an affordable inexpensive raw material for technologies of electronics and photovoltaics

Based on the analysis of modern methods for obtaining semiconductor silicon, critical factors influencing the prospects for the development of the industry are identified. The basic component of the production scheme for producing silicon of semiconductor quality today is the carbothermal technology for producing metallurgical silicon. The dominance of this scheme is largely dictated by economic reasons for the development of capital-intensive industries. The accumulation of objective needs over time predetermine the need to overcome the inertial barrier of evolutionary steps in the development of semiconductor quality silicon technology.
 First of all, the problems of raw material supply and high energy intensity of traditional production processes are actualized. The task is formulated in the direction of searching for a source of raw materials that removes in the time perspective the problems of ensuring a potential increase in the volume of production of semiconductor quality silicon, as well as the problems of energy supply for this growth process. As a promising solution, a method is proposed for obtaining silicon of semiconductor quality directly from quartz sand, excluding the use of expensive and scarce quartzites and charcoal. The prospects for quartz sand as a raw material replacing quartzite are objectively predetermined by the high similarity of the physicochemical characteristics of these materials. The objective prerequisites for the process of replacing quartzite are supported by the existing practice of testing the proposed technological solutions on an industrial scale.For this purpose, low energy-intensive processes for the production and purification of silanes, utilization and reversal of intermediate technological products are used. The energy efficiency of the method is ensured by the exclusion from the technology of a large-tonnage, energy-intensive process for obtaining metallurgical silicon, as well as energy-consuming methods associated with the use of low temperatures (–30 ... –80 ° C). The technological solution eliminates the need for the synthesis of hydrogen chloride and, accordingly, eliminates the explosive high-temperature process from production. The proposed solutions open up possibilities for the variable use of known technologies in relation to the current consumer requirements for the quality of polycrystalline silicon.

Integration of Self-Passivated Topological Electrodes for Advanced 2D Optoelectronic Devices.

With the rapid development of two-dimensional semiconductor technology, the inevitable chemical disorder at a typical metal-semiconductor interface has become an increasingly serious problem that degrades the performance of 2D semiconductor optoelectronic devices. Herein, defect-free van der Waals contacts have been achieved by utilizing topological Bi2 Se3 as the electrodes. Such clean and atomically sharp contacts avoid the consumption of photogenerated carriers at the interface, enabling a markedly boosted sensitivity as compared to counterpart devices with directly deposited metal electrodes. Typically, the device with 2D WSe2 channel realizes a high responsivity of 20.5AW-1 , an excellent detectivity of 2.18×1012 Jones, and a fast rise/decay time of 41.66/38.81ms. Furthermore, high-resolution visible-light imaging capability of the WSe2 device is demonstrated, indicating its promising application prospect in future optoelectronic systems. More inspiringly, the topological electrodes are universally applicable to other 2D semiconductor channels, including WS2 and InSe, suggesting its broad applicability. These results open fascinating opportunities for the development of high-performance electronics and optoelectronics.

Porous Si loaded with Ag nanoparticles for ultra-broadband infrared absorption and detection

With the rapid development of semiconductor technology, silicon based infrared detector chips have been greatly optimized with the help of MEMS process. The infrared absorber, as the core part of thermal detector, requires infrared absorption characteristics such as wide spectrum and high absorption. In this paper, two kinds of porous silicon materials loaded with Ag nanoparticles (Si@AgNPs), honeycomb-like and forest-like, were constructed by chemical etching method. The experimental results and corresponding analyses illustrated that micro- and nano-porous structures of silicon with arbitrary sizes and random spatial positions can have a great guiding effect on the light waves, providing multiple reflections and scattering, allowing increased light propagation paths and generating light trapping effect, leading to enhanced infrared absorption in a wide spectral range. AgNPs are loaded, and the collective oscillation of free electrons resonates with incident photons, thereby exciting plasmon resonance effect, which can further improve the infrared absorption properties of the material. Benefiting from the synergistic effect of light trapping and plasmon resonance, the porous Si@AgNPs with honeycomb-like or forest-like structure both exhibited high absorption properties at 2.5–20 μm. Moreover, the honeycomb-like Si@AgNPs also possessed optical interference effect, which can further enhance the absorption, compared with the forest-like Si@AgNPs.

Active and Programmable Metasurfaces with Semiconductor Materials and Devices

Active metasurfaces provide promising tunabilities to artificial meta−atoms with unnatural optical properties and have found important applications in dynamic cloaking, reconfigurable intelligent surfaces, etc. As the development of semiconductor technologies, electrically controlled metasurfaces with semiconductor materials and devices have become the most promising candidate for the dynamic and programmable applications due to the large modulation range, compact footprint, pixel−control capability, and small switching time. Here, a technical review of active and programmable metasurfaces is given in terms of semiconductors, which consists of metasurfaces with diodes, transistors, and newly rising semiconductor materials. Physical models, equivalent circuits, recent advances, and development trends are discussed collectively and critically. This review represents a broad introduction for readers just entering this interesting field and provides perspective and depth for those well−established.

Heterogeneous Integration of Atomically-Thin Indium Tungsten Oxide Transistors for Low-Power 3D Monolithic Complementary Inverter.

In this work, the authors demonstrate a novel vertically-stacked thin film transistor (TFT) architecture for heterogeneously complementary inverter applications, composed of p-channel polycrystalline silicon (poly-Si) and n-channel amorphous indium tungsten oxide (a-IWO), with a low footprint than planar structure. The a-IWO TFT with channel thickness of approximately 3-4 atomic layers exhibits high mobility of 24 cm2 V-1 s-1 , near ideally subthreshold swing of 63mV dec-1 , low leakage current below 10-13 A, high on/off current ratio of larger than 109 , extremely small hysteresis of 0mV, low contact resistance of 0.44 kΩ-µm, and high stability after encapsulating a passivation layer. The electrical characteristics of n-channel a-IWO TFT are well-matched with p-channel poly-Si TFT for superior complementary metal-oxide-semiconductor technology applications. The inverter can exhibit a high voltage gain of 152V V-1 at low supply voltage of 1.5V. The noise margin can be up to 80% of supply voltage and perform the symmetrical window. The pico-watt static power consumption inverter is achieved by the wide energy bandgap of a-IWO channel and atomically-thin channel. The vertically-stacked complementary field-effect transistors (CFET) with high energy-efficiency can increase the circuit density in a chip to conform the development of next-generation semiconductor technology.

A Study on the Control Method of 6-DOF Magnetic Levitation System Using Non-Contact Position Sensors

Recently, due to the development of semiconductor technology, high-performance memory and digital convergence technology that integrates and implements various functions into one semiconductor chip has been regarded as the next-generation core technology. In the semiconductor manufacturing process, various motors are being applied for automated processes and high product reliability. However, dust and shaft loss due to mechanical friction of a general motor system composed of motor-bearing are problematic for semiconductor wafer processing. In addition, in the edge bread remove (EBR) process after the photoresist application process, a nozzle position control system for removing unnecessary portions of the wafer edge is absolutely necessary. Therefore, in this paper, in order to solve the problems occurring in the semiconductor process, a six-degrees-of-freedom (6-DOF) magnetic levitation system without shaft and bearing was designed for application to the semiconductor process system; and an integrated driving control algorithm for 6-DOF control (levitation, rotation, tilt (Roll-Pitch), X-Y axis movement) using the force of each current component derived through current vector control was proposed. Finally, the 6-DOF magnetic levitation system with the non-contact position sensors was fabricated and the validity of the 6-DOF magnetic levitation control method proposed in this paper was verified through a performance test using a prototype.

A novel TMOSFET ternary inverter based on hybrid conduction mechanism

With the development of complementary metal-oxide semiconductor (CMOS) technology, the feature size of mental-oxide-semiconductor field-effect-transistor (MOSFET) is continuously shrunk, the short channel effect becomes more and more serious, which makes the static power consumption increase, and now the static power consumption becomes a main source of the power consumption of the integrated circuits. Currently, the performance of CMOS binary logic processor is approaching a bottleneck; therefore the ternary logic becomes a research hotspot to promote the development of high-performance low-power integrated circuits. Compared with binary logic, ternary logic possesses a strong data expression capability, which can not only improve the data density, but also reduce the circuit power consumption and the system complexity. However, using binary devices to build ternary logic circuits requires a large number of components, and even the passive components, which makes it impossible to leverage the advantages of ternary logic. The other method of implementing ternary logic is to utilize innovative two-dimensional materials. This method requires a small number of components and obviates the need for passive components, but it faces the problem that the fabrication process is not mature and cannot be mass-produced. To solve these problems, in this paper by combining the tunneling and the drift diffusion mechanism, we propose a tunneling metal-oxide-semiconductor field-effect transistor (TMOSFET) with three-state characteristics that make it highly suitable for ternary logic design. Compared with other ternary logic schemes, the ternary inverter based on TMOSFET has the same circuit structure as binary inverter, which can simplify the circuit design. In this paper, the operational mechanism of this ternary inverter is studied, and the condition of three-state output of inverter is analyzed. It is found that when the operating voltage <i>V</i><sub>DD</sub> and the device turning voltage <i>V</i><sub>turn</sub> satisfy <i>V</i><sub>DD</sub>/<i>V</i><sub>turn</sub> ≈ 1.4, the input voltage ranges of the three output states are equivalent. In addition, the influence of TMOSFET transfer characteristic on this ternary inverter is also analyzed. This has certain reference significance for designing and studying ternary logic circuits in future.

Wiley‐SID Volume Delivers Latest Developments in Transparent Oxide Semiconductor Technology

AMORPHOUS OXIDE SEMIconductors (AOS) are a class of electronic materials that has seen significant rapid developments. Their success in the market is secured by the synergistic effects arising between favorable material properties and the ability to control them, a good understanding of the underlying properties that govern the electronic behavior, comparatively straightforward and economical processing, and a receptive audience in the information display community. These materials have helped satisfy the need for lower power consumption, higher brightness, faster refresh rates, and higher resolution. It is not surprising that they have rapidly established a strong position in the emerging field of high-performance portable and large-area displays. With the pace of this technical innovation showing no sign of wavering, pioneering researchers and editors Hideo Hosono and Hideya Kumomi have assembled contributions from more than 50 experts to produce a comprehensive reference text, Amorphous Oxide Semiconductors: IGZO and Related Materials for Display and Memory, in the Wiley-SID book series. The book's subtitle hints at the large family of highly versatile properties and focuses primarily on displays and memory. It emphasizes current leading applications, while also featuring a discussion of broader uses where it is most relevant or instructive. Structured in eight parts, the book begins with chapters that provide a valuable overview of the history, physical and electronic structures of oxide semiconductors, along with their properties in comparison to silicon and the need for applications. A major section follows on fundamentals covering material properties and structure, defects, doping, and conduction. This solid foundation provides an essential understanding for the sections that follow: informative chapters on processing, with a focus on synthesis, solution processing for flexible electronics, and recent advances in atomic layer deposition with applications for thin-film transistors (TFTs) using a variety of active materials. This segues into a handful of chapters on all aspects of transistor design and usage: treating high-performance bulk accumulation and elevated-metal TFT architectures, the origin and control of instabilities, modeling and simulation, and matters concerning oxide TFT applicability to flexible electronics and signal-processing arrays. The final two parts cover state-of-the-art applications and new materials. Applications focus mostly on displays, including those realized with printed techniques, imagers, and memory. These are complemented by chapters on backend line integration of oxide TFTs and neuromorphic chips using AOS devices, which introduce a wide range of future and emerging applications and techniques that lie outside of traditional areas. The section on materials covers light-emitting diodes, electroluminescent displays, and vertical-cavity surface-emitting lasers, as well as high-mobility AOS and progress in p-type materials for TFTs. The broad range of activity presented in both materials and applications is encouraging and confirms that where some applications have reached full technical maturity, there is significant room for development as well as an interest in broader uses. A careful examination of the sections revealed a measure of overlap in information among different chapters. However, given the breadth of applications covered, a degree of repetition on the basics of material and transport properties is unavoidable. For students or those less experienced in the field, it presents an opportunity to assimilate major themes through the viewpoints of several expert authors. In this regard, the book does an excellent job of reinforcing and subtly complementing the critical notions, repeatedly relating materials, process conditions, and structure to electrical performance. Most chapters have ample and relevant reference lists, including numerous milestone publications that will provide useful starting points for future literature searches as the field evolves. AOS is demonstrably successful and highly promising in diverse applications. Processing versatility allows for the realization of flexible electronic systems, and recent advances in controlling layers and interfaces are yielding highly efficient and low-operating-voltage devices. The editors demonstrate that the range of AOS applications likely will expand significantly, not only in the stated areas of displays and memories, but promisingly beyond. The book serves as a valuable reference for traditional applications and as a landmark in the development of these versatile electronic materials. The text is easy to navigate and rich in detailed information, which should satisfy a wide readership in both academia and industry at various levels of experience. Radu A. Sporea is a lecturer in power electronics and semiconductor devices at the Advanced Technology Institute, University of Surrey.