Development Of ASIC Research Articles

The optimization, design and performance of the FBCM23 ASIC for the upgraded CMS beam monitoring system

We present the development of the FBCM23 ASIC designed for the Phase-II upgrade of the Fast Beam Condition Monitoring (FBCM) system built at the CMS experiment which will replace the present luminometer based on the BCM1F ASIC [1]. The FBCM system should provide reliable luminosity measurement with 1 ns time resolution enabling the detection of beam-induced background. The FBCM23 ASIC comprises 6 channels of the fast front-end amplifier working in transimpedance configuration, booster amplifier, and leading edge discriminator. The complete processing chain provides an overall shaping function equivalent to the CR-RC3 filter. The paper will show the optimization of the design, overall architecture, and the detailed implementation in a CMOS 65 nm process as well as preliminary electrical performance.

Review on the FPGA design optimization for ASIC

FPGA is a product of further development on programmable devices such as PAL and GAL. It is not only a chip, but a design pattern. With the rapid growth in FPGA performance and density, its complete top-down model can be applied to the development of similar ASICs while improving the technology itself. This paper shows that a summary analysis of previous articles can conclude that the application of FPGA design to ASICs can lead to optimization of many aspects. Architecture-level embedding and mapping transformation are the current mainstream application methods, both of which can bring strong economic and time benefits. Meanwhile, there are various issues that need special consideration in the application process which is related to the question of whether or not to map and convert. Finally, according to the analysis, we still need to solve two important issues which are the lack of automatic mapping tools and the lack of a unified function library in the future.

ASICs for LHC intermediate tracking detectors

The tracking detectors proposed for the LHC were unprecedented in their size and operational requirements, especially radiation tolerance and data rates. When they were first envisaged it was uncertain that technologies would be available which would meet the specifications, and considerable R&D was necessary to demonstrate this. In particular, customised electronic integrated circuits were evidently essential, yet they were probably technologically the least certain components. The radiation levels and the readout rates in earlier generations of collider experiments were far below those required for the LHC trackers and the number of LHC readout chips required was much larger. Nevertheless, solutions were eventually found, which continue to function reliably with excellent performance. In many ways, the tracker ASIC developments laid foundations and blazed trails for chips later designed for many other sub-detector systems.The ATLAS and CMS trackers developed different solutions to the LHC challenges, and are representative of other LHC systems. This review focuses on the ASIC developments undertaken by these two experiments to explain the most important innovations, recent progress and future challenges.The term “intermediate tracking detectors” is meant to differentiate from the innermost trackers close to the beam pipe and interaction region. This region is served by pixel detectors, whose development began later than the LHC trackers discussed here.

The Q-Pix pixelated readout concept for future Liquid Argon Time Projection Chambers: status and prospects.

Future long baseline neutrino experiments such as the Deep Underground Neutrino Experiment (DUNE) pose challenges for development of readout techniques for multi-kiloton LAr Time Projection Chambers (TPCs). In contrast to wire/strip anode readout, a pixelated readout eliminates disadvantages such as disambiguation in 2D track reconstruction. The Q-Pix Consortium, established in 2019, is developing a pixelated readout technique for LAr TPCs based on charge-integrate/reset (CIR) circuits. The CIR blocks generate a sequence of reset pulses with time intervals corresponding to fixed charge integrals, allowing signal reconstruction without continuous digitization. The Q-Pix ASIC, intended for reading out pixel arrays, comprises CIR blocks along with digital components responsible for communication and reconfigurable data routing. This work is devoted to give an overview of the Q-Pix project, its status, and prospects, with emphasis on the development and prototyping of the Q-Pix readout ASICs.

Low-Noise Analog Channel for the Readout of the Si(Li) Detector of the GAPS Experiment

This work is focused on the design and the experimental characterization of an analog channel developed for the readout of lithium-drifted silicon detectors of the General AntiParticle Spectrometer (GAPS) experiment aimed at the search for dark matter. The instrument is designed for the identification of antideuteron particles from cosmic rays during an Antarctic balloon mission scheduled for late 2022. A low-noise analog front-end, featuring a dynamic signal compression to comply with the wide input range, has been designed in commercial 180-nm CMOS technology. The channel was fabricated in 2018 and is the first building block toward the development of a multichannel readout ASIC. The article will provide a description of the design criteria, the architecture of the channel, and a summary of the results of the experimental characterization.

Development of a low-noise front-end ASIC for CdTe detectors

We present our latest ASIC, which is used for the readout of Cadmium Telluride double-sided strip detectors (CdTe DSDs) and high spectroscopic imaging. It is implemented in a 0.35 μm CMOS technology (X-Fab XH035), consists of 64 readout channels and has a function that performs simultaneous AD conversion for each channel. The equivalent noise charge of 54.9e−± 11.3e− (rms) is measured without connecting the ASIC to any detectors. From the spectroscopy measurements using a CdTe single-sided strip detector, the energy resolution of 1.12 keV (FWHM) is obtained at 13.9 keV, and photons within the energy from 6.4 keV to 122.1 keV are detected. Based on the experimental results, we propose a new low-noise readout architecture making use of a slew-rate limited mode at the shaper followed by a peak detector circuit.

Development of a low power and high integration readout ASIC for time projection chambers in 65 nm CMOS

The paper presents the development of a low power readout ASIC for time projection chambers (TPCs) for the CEPC (Circular Electron Positron Collider) experiments. In order to achieve high spatial and momentum resolution, large number of readout channels is demanded with waveform sampling capability in the resolution of 8-10 bit and the sampling rate of 10-40 MS/s. Power consumption became critical and has been addressed by using advanced 65 nm CMOS process and simplifying the analog circuits in our design. The prototype chip has been developed including the analog front-end and the waveform sampling SAR (Successive Approximation Register) ADC. This paper will present the detailed circuit design and test results. The development of the digital trapezoidal filter will also be described.

Development of a pixel readout ASIC for CZT detectors for spectral X-ray photon-counting imaging applications

This paper presents the development of a prototype pixel readout ASIC for CZT detectors fabricated in a 180 nm CMOS process. It consists of a 32 × 32 array of pixels in 100 μm pitch and the EOC (end-of column) circuit for control and data readout. Each pixel integrates a charge sensitive preamplifier, a CR-RC shaper, two discriminators, two 12-bit counters and registers, allowing us to acquire and readout images simultaneously. A local 6-bit register has also been integrated for each pixel for calibration enable and threshold fine tuning, which can be programmed through a SPI slow control interface. A dedicated chip evaluation system was developed and the initial test results showed that the chip worked well. The power consumption was measured to be 38.9 μW per pixel, which could be adjusted by the master bias unit. The gain of the analog front-end was approximately 77.3 mV/fC and the ENC was less than 100 electrons for different shaping times and the input capacitance of about 100 fF. The results were in good agreement with our design specifications. More detailed design and test results will be discussed in this paper.

Intelligent and Analog CMOS ASIC Development of Angular Rate Error Compensation for MEMS Gyroscope

Background & Objective: MEMS-based gyroscopes are used in angular rate detection where precision is an important parameter; however, gyroscope output is limited by angular rate error. For minimizing these types of non-idealities, conventional external hardware-based analog or digital circuits have limitations for using in compact applications. CMOS analog ASIC for angular rate error compensation is necessary as both MEMS-CMOS technologies are supplementary and compatible. Method: In this paper, the output of MEMS gyroscope is taken as input for the compensation circuit which results in compensated angular rate. ANN is used in intelligent compensation circuit for error reduction in which offline data is trained and minimum optimum error of MSE of 1.72e-4 is achieved. ANN uses tanh sigmoidal activation function and back propagation trained MLP model with three neurons in the hidden layer. The equivalent ANN is implemented by CMOS ASIC where each neuron is implemented using Gilbert multiplier cell, differential analog adder, and differential amplifier as tanh sigmoidal circuit using OrCAD-PSpice 10.5 with 0.35 μ m technology. These blocks consist of differential configuration which has the capability of common mode interference rejection as noise becomes comparable at lower values of input analog signal. The entire ASIC consumes 77.8 mW of power which is far less and compact in size as compared to available external hardware interface circuits. Result and Conclusion: MEMS gyroscope with proposed analog ASIC becomes smart sensor with ANN based intelligent interface circuit. The proposed compensation cum interface circuit gives the average angular rate error of 1.91% in the range of minimum 0% to maximum 27% leading to improved accuracy.

ATLAS LAr calorimeter performance in LHC run 2 and electronics upgrades for next runs

Liquid argon (LAr) sampling calorimeters are employed by ATLAS for all electromagnetic calorimetry in the pseudo-rapidity region |η|<3.2, and for hadronic and forward calorimetry in the region from |η|=1.5 to |η|=4.9. In the LHC Run 2 about 150 fb−1 of data at a center-of-mass energy of 13 TeV have been recorded. The well calibrated and highly granular LAr Calorimeter reached its design values both in energy measurement as well as in direction resolution. Electronics developments are pursued for the trigger readout of the ATLAS LAr Calorimeter towards the Phase-I upgrade scheduled in the LHC shut-down period between December 2018 and early 2021. Trigger signals with finer spatial granularity and higher precision are needed in order to improve the identification efficiencies of electrons, photons, taus, jets and missing energy, at high background rejection rates, already at the Level-1 trigger. Following new TDAQ buffering requirements and high expected radiation doses in the pileup conditions of the high-luminosity LHC, the LAr Calorimeter electronics will be further upgraded (Phase-II) to readout the full 182,500 calorimeter cells at 40 MHz with 16 bit dynamic range. Developments of low-power preamplifiers and shapers to meet these requirements are ongoing in 130 nm CMOS. In order to digitize the analogue signals on two gains after shaping, radiation-hard, low-power 40 MHz 14-bit ADCs are developed using a SAR architecture in 65 nm CMOS. This contribution gives an overview of the detector operation, changes in the monitoring and data quality procedures, to cope with increased pileup, as well as the achieved performance. Results of ASIC developments including quality assurance and quality control (QA/QC) and radiation hardness evaluations, performances of the pre-production boards and results of the system integration tests, progress of QA/QC of final production boards are presented along with the overall system design for the Phase-I upgrade. Results of tests of the first prototypes of front-end components are presented, along with design studies on the performance of the off-detector readout system for the Phase-II upgrade.

The Phase-1 Trigger Readout Electronics Upgrade of the ATLAS Liquid Argon Calorimeter

Electronics developments are pursued for the trigger readout of the ATLAS Liquid-Argon Calorimeter towards the Phase-I upgrade scheduled in the LHC shut-down period of 2019-2020. The LAr Trigger Digitizer system will digitize 34,000 channels at a 40 MHz sampling with 12 bit precision after the bipolar shaper at the front-end system, and transmit to the LAr Digital Processing system in the back-end to extract the transverse energies. Results of ASIC developments including quality assurance and radiation hardness evaluations, performances of the nal prototypes and results of the system integration tests will be presented along with the overall system design.

DIET: a multi-channel SiPM readout ASIC for TOF-PET with individual energy and timing digitizer

Monolithic scintillator detectors readout by silicon photomultiplier arrays can achieve favorable timing and spatial resolution in three dimensions and hence may significantly improve the sensitivity of PET and TOF-PET systems. This paper presents the development of a 64-channel SiPM readout ASIC, named DIET, with individual amplification and digitization of both energy and timing information. The chip performance such as input range and resolution were optimized for continuous LYSO crystal readout. The digitizer was implemented by a time-to-amplitude converter and a 10-bit Wilkinson type analog-to-digital converter. An automatic calibration method was proposed and implemented based on the timing distribution of SiPM dark counts. A prototype ASIC was fabricated in 0.18 μm CMOS process with the die area of 3 × 3 mm2. The chip was fully evaluated. For the energy measurement, the INL and noise was measured to be less than 0.6% and 0.88% respectively. For the timing measurement, the bin size of the time digitizer was measured to be 25 ps and the DNL of less than 0.45 LSB. The time resolution of 63.6 ps FWHM in single channel has been achieved for 20 p.e. signals at 0.5 p.e. threshold. The power consumption of the chip was less than 5 mW per channel. The chip was also tested with LYSO crystals (2 mm × 2 mm × 11 mm) coupled to SensL SiPMs after calibration with the dark counts. The energy resolution of 511 keV peak was measured to be 12.6% FWHM and the CRT of 334 ps FWHM was achieved.

Development of a low-noise readout ASIC for Silicon Drift Detectors in high energy resolution X-ray spectrometry

ASIC with a low-noise readout channel for Silicon Drift Detectors in high energy resolution X-ray spectrometry was designed and prototyped in the AMS 350 nm CMOS process via Europractice as a miniASIC. For the analog readout channel tests there was used the detector module SDD-10-130-PTW LTplus-ic (PNDetector GmbH). The measured energy resolution of this module with the designed readout channel: 200 eV (FWHM) at 55Fe, -16 °C, 1 kcps and a peaking time of 8 μs.

KLauS: a low power Silicon Photomultiplier charge readout ASIC in 0.18 UMC CMOS

We present the development of a low power Silicon Photomultiplier charge readout ASIC for an imaging calorimeter at a future linear collider. The analog front-end is designed to achieve sufficient signal-to-noise ratio for single pixel signals using low gain SiPMs, while allowing charge measurements over the full dynamic range of the sensors. The front-end consists of an input stage, two charge measurement branches and a fast comparator. A SAR ADC with a resolution of 10 bit digitizes the pulse height information. An additional pipelined SAR stage allows to increase the quantization resolution to 12 bit for calibration measurements.

A low-noise 64-channel front-end readout ASIC for CdZnTe detectors aimed to hard X-ray imaging systems

In this paper, we report on the recent development of a 64-channel low-noise front-end readout ASIC for CdZnTe detectors aimed to hard X-ray imaging systems. The readout channel is comprised of a charge sensitive amplifier, a leakage current compensation circuit, a CR-RC shaper, two S–K filters, an inverse proportional amplifier, a peak-detect-and-hold circuit, a discriminator and trigger logic, a time sequence control circuit and a driving buffer. The readout ASIC is implemented in TSMC 0.35μm mixed-signal CMOS technology, the die size of the prototype chip is 2.7mm×8.0mm. The overall gain of the readout channel is 200mV/fC, the power consumption is less than 8 mW/channel, the linearity error is less than 1%, the inconsistency among the channels is less than 2.86%, and the equivalent noise charge of a typical channel is 66 e− at zero farad plus 14 e− per picofarad. By connecting this readout ASIC to an 8×8 pixel CdZnTe detector, we obtained an energy spectrum, the energy resolution of which is 4.5% at the 59.5keV line of 241Am source.

Development of the read-out ASIC for muon chambers

A front-end prototype ASIC for muon chambers is presented. ASIC was designed and prototyped in the CMOS UMC MMRF 180 nm process via Europractice. The chip includes 8 analog processing channels, each consisting of a preamplifier, two shapers (fast and slow), differential comparator and an area efficient 6 bit SAR ADC with 1.2 mW power consumption at 50 Msps. The chip also includes the threshold DAC and digital serializer. The design has the following features: dynamic range of 100 fC, channel hit rate of 2 MHz, ENC of 1000 e- at 50 pF, power consumption of 10 mW per channel, 6 bit SAR ADC.

Development and experimental study of the readout ASIC for muon chambers of the CBM experiment

The measurement results of the front-end ASIC for the GEM detector read-out are presented. The MUCH ASIC v2 was designed and prototyped via Europractice by means of the 0.18 um CMOS MMRF process of UMC (Taiwan). The parameters of the analog channels, including the CSA, fast and slow shapers, discriminators, were measured. The channels provide a sufficient dynamic range of 100 fC, low power consumption of 10 mW per channel and ENC of 1550 el at a 50 pF detector capacitance.

Architecture of the multichannel data-driven ASIC

The development architecture of a multichannel data-driven ASIC is presented. It provides the selection of useful events at an early stage of reading out detector signals. The architecture is based on fast cross-point switches of analog signals, followed by their digitization by a limited set of ADCs and high-speed output data serialization. Such approach reduces the number of subsequent ADCs as well as digital processing channels. That leads to lower power consumption and chip area. The results of a prototype ASIC development, based on this architecture and intended for the CBM experiment at FAIR, are given.

Design of a Multi-Channel Low-Noise Readout ASIC for CdZnTe-Based X-Ray and &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$\gamma $&lt;/tex&gt;&lt;/formula&gt;-Ray Spectrum Analyzer

In this paper, we report on the recent development of a 32-channel low-noise front-end readout ASIC for cadmium zinc telluride (CdZnTe) X-ray and $\gamma $ -ray detectors. Each readout channel includes a charge sensitive amplifier, a CR-RC shaping amplifier and an analog output buffer. The readout ASIC is implemented using TSMC $0.35 - \mu \hbox{m}$ mixed-signal CMOS technology, the die size of the prototype chip is $2.2~\hbox{mm} \times 4.8~\hbox{mm}$ . At room temperature, the equivalent noise level of a typical channel reaches $133~\hbox{e}^ - ({\rm rms})$ with the input parasitic capacitance of 0 pF for the average power consumption of 2.8 mW per channel. The linearity error is less than $ \pm 2\% $ and the input energy dynamic range of the readout ASIC is from 10 keV to 1 MeV. The crosstalk between the channels is less than 0.4%. By connecting the readout ASIC to a CdZnTe detector, we obtained a $\gamma $ -ray spectrum, the energy resolution is 1.8% at the 662-keV line of $^{137}{\rm Cs}$ source.

Development of the read-out ASIC for muon chambers of the CBM experiment

A front-end ASIC for GEM detectors readout in the CBM experiment is presented. The design has the following features: dynamic range of 100 fC, channel hit rate of 2 MHz, ENC of 1000 e- at 50 pF, power comsumption of 10 mW per channel, 6 bit SAR ADC. The chip includes 8 analog processing chains, each consisting of preamplifier, two shapers (fast and slow), differential comparator and an area efficient 6 bit SAR ADC with 1.2 mW power consunption at 50 Msps. The chip also includes the threshold DAC and the digital part.