Development of a low power and high integration readout ASIC for time projection chambers in 65 nm CMOS

Abstract

The paper presents the development of a low power readout ASIC for time projection chambers (TPCs) for the CEPC (Circular Electron Positron Collider) experiments. In order to achieve high spatial and momentum resolution, large number of readout channels is demanded with waveform sampling capability in the resolution of 8-10 bit and the sampling rate of 10-40 MS/s. Power consumption became critical and has been addressed by using advanced 65 nm CMOS process and simplifying the analog circuits in our design. The prototype chip has been developed including the analog front-end and the waveform sampling SAR (Successive Approximation Register) ADC. This paper will present the detailed circuit design and test results. The development of the digital trapezoidal filter will also be described.