Deterministic Random Bit Research Articles

Enhanced ARIA-based counter mode deterministic random bit generator random number generator implemented in verilog

This paper presents a study aimed at effectively implementing a deterministic random bit generator (DRBG) IP in verilog language, based on the standard encryption algorithm. By controlling the existing round generation and key generation blocks, the internal modules of the counter mode deterministic random bit generator (CTR-DRBG) were successfully implemented and operated, ensuring the secure and efficient generation of random bit sequences. The research focused on parallel operation of modules and optimized module placement to achieve improved clock frequencies. By concurrently operating two modules in the derivation and internal update modules of CTR-DRBG, the processing speed was enhanced compared to the conventional algorithm. Additionally, integrating the reseeding and initialization modules of CTR-DRBG into a single module successfully reduced size. Furthermore, this IP supports the special function register (SFR) interface. The safety of the CTR-DRBG was validated through known answer test (KAT) verification utilizing test vectors from certification. Future research should explore additional studies on CTR-DRBG operating on real FPGA or ASIC, not only using normal algorithm but also employing other block cipher algorithms.

XDRBG: A Proposed Deterministic Random Bit Generator Based on Any XOF

A deterministic random bit generator (DRBG) generates pseudorandom bits from an unpredictable seed, i.e., a seed drawn from any random source with sufficient entropy. The current paper formalizes a security notion for a DRBG, in which an attacker may make any legal sequence of requests to the DRBG and sometimes compromise the DRBG state, but should still not be able to distingush DRBG outputs from ideal random bits. The paper proposes XDRBG, a new DRBG based on any eXtendable Output Function (XOF) and proves the security of the XDRBG in the ideal-XOF model. The proven bounds are tight, as demonstrated by matching attacks. The paper also discusses the security of XDRBG against quantum attackers. Finally, the paper proposes concrete instantiations of XDRBG, employing either the SHAKE128 or the SHAKE256 XDRBG. Alternative instantiations suitable for lightweight applications can be based on ASCON.

Generation of 1 GB full entropy random numbers with the enhanced-NRBG method

Random numbers have significant applications in fundamental science, high-level scientific research, cryptography and several other areas where there is a pressing need for high-quality random numbers. We present an experimental demonstration of a non-deterministic random bit generator from a quantum entropy source and a deterministic random bit generator mechanism to provide high quality random numbers of 1 GB data size. Quantum entropy is realized by a series of quantum chips based on radioactive isotope Americium-241. The extracted raw random numbers are further post-processed to generate a high-entropy seed for the hash based deterministic random bit generator. We discuss the implementation of randomness extraction algorithm and Hash-DRBG algorithm in detail. The random numbers pass all the randomness measures provided in standard statistical test suites.

Secured computed tomography scanner using a random bit.

Patient data in current computed tomography scanner machines are transferred through several communication channels, such as WiFi, to the mobile channel platform. Therefore, patient information is an important security concern. Medical imaging must be protected using various methods. The current hardware-dependent method for generating random bits exhibits predictable or inconvenient physical characteristics. Therefore, a more flexible random-bit generation technique is to be devised. We propose a deterministic random bit generation algorithm that uses a mathematical periodic function. After randomizing the image using the proposed random bit, the performance is analyzed and compared with that of the processed image. The random bit generation method using a mathematical algorithm shows higher entropy than the random bit generated by hardware.

Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source.

In the cybersecurity field, the generation of random numbers is extremely important because they are employed in different applications such as the generation/derivation of cryptographic keys, nonces, and initialization vectors. The more unpredictable the random sequence, the higher its quality and the lower the probability of recovering the value of those random numbers for an adversary. Cryptographically Secure Pseudo-Random Number Generators (CSPRNGs) are random number generators (RNGs) with specific properties and whose output sequence has such a degree of randomness that it cannot be distinguished from an ideal random sequence. In this work, we designed an all-digital RNG, which includes a Deterministic Random Bit Generator (DRBG) that meets the security requirements for cryptographic applications as CSPRNG, plus an entropy source that showed high portability and a high level of entropy. The proposed design has been intensively tested against both NIST and BSI suites to assess its entropy and randomness, and it is ready to be integrated into the European Processor Initiative (EPI) chip.

Chaining Optimization Methodology: A New SHA-3 Implementation on Low-End Microcontrollers

Since the Keccak algorithm was selected by the US National Institute of Standards and Technology (NIST) as the standard SHA-3 hash algorithm for replacing the currently used SHA-2 algorithm in 2015, various optimization methods have been studied in parallel and hardware environments. However, in a software environment, the SHA-3 algorithm is much slower than the existing SHA-2 family; therefore, the use of the SHA-3 algorithm is low in a limited environment using embedded devices such as a Wireless Sensor Networks (WSN) enviornment. In this article, we propose a software optimization method that can be used generally to break through the speed limit of SHA-3. We combine the θ, π, and ρ processes into one, reducing memory access to the internal state more efficiently than conventional software methods. In addition, we present a new SHA-3 implementation for the proposed method in the most constrained environment, the 8-bit AVR microcontroller. This new implementation method, which we call the chaining optimization methodology, implicitly performs the π process of the f-function while minimizing memory access to the internal state of SHA-3. Through this, it achieves up to 26.1% performance improvement compared to the previous implementation in an AVR microcontroller and reduces the performance gap with the SHA-2 family to the maximum. Finally, we apply our SHA-3 implementation in Hash_Deterministic Random Bit Generator (Hash_DRBG), one of the upper algorithms of a hash function, to prove the applicability of our chaining optimization methodology on 8-bit AVR MCUs.

Efficient Implementation of AES and CTR_DRBG on 8-Bit AVR-Based Sensor Nodes

Since Rijndael algorithm was selected as the Advanced Encryption Standard (AES) by NIST, optimization research for the AES has been actively conducted on various IoT-based processors. In an 8-bit AVR environment, LIGHT version of Fast AES CTR-mode Encryption (FACE-LIGHT) was proposed at ICISC'2019 conference. However, in a Wireless Sensor Network environment, where sessions are frequently changed, FACE-LIGHT seems not efficient in terms of available memory and generating a pre-computation table. In this article, we present a new column-wise fashion implementation. Unlike previous best AES implementations, our proposed implementation in an 8-bit AVR microcontroller combines SubBytes, ShiftRows, and MixColums operations and optimizes the operation speed through efficient register scheduling. Our constant-time implementation uses a significantly less table than FACE-LIGHT in an 8-bit AVR microcontroller, achieving 2,251, 2,706, and 3,160 clock cycles when encrypting 128-bit data for each of three security levels. In particular, our 256-bit security level AES implementation is the fastest AES implementation as far as we know in 8-bit AVR microcontroller. Finally, we apply our implementation in CounTeR-mode_Deterministic Random Bit Generator (CTR_DRBG), one of the upper algorithms of a symmetric-key algorithm, to prove the generality of our optimization technology in various operating modes of AES.

Trojan Attack on the Initialization of Pseudo-Random Bit Generators Using Synchronization of Chaotic Input Sources

An initialization input attack on a set of two pseudo-random generators using analog-digital hardware Trojan is presented in this paper. Trojan circuit implementations are discussed following their full classification. Simulation results confirming the effectiveness of the Trojan impact on a repetition of identical seed values are analyzed. Trojan structure is integrated with the deterministic random bit generator functional model recommended by NIST and the task is to impact two seed generators (in two channels), which use the independent Chua circuits as the sources of entropy. The analog Trojan part causes synchronization of the two analog chaotic circuits as explained by the results of LTSpice simulation. The digital Trojan part controls the analog part and modifies the values of optional parameters used in the creation of the seeds. The seed value creation in two cases (with and without Trojan) are simulated by using Xilinx ISIM.

Parallel Implementations of ARX-Based Block Ciphers on Graphic Processing Units

With the development of information and communication technology, various types of Internet of Things (IoT) devices have widely been used for convenient services. Many users with their IoT devices request various services to servers. Thus, the amount of users’ personal information that servers need to protect has dramatically increased. To quickly and safely protect users’ personal information, it is necessary to optimize the speed of the encryption process. Since it is difficult to provide the basic services of the server while encrypting a large amount of data in the existing CPU, several parallel optimization methods using Graphics Processing Units (GPUs) have been considered. In this paper, we propose several optimization techniques using GPU for efficient implementation of lightweight block cipher algorithms on the server-side. As the target algorithm, we select high security and light weight (HIGHT), Lightweight Encryption Algorithm (LEA), and revised CHAM, which are Add-Rotate-Xor (ARX)-based block ciphers, because they are used widely on IoT devices. We utilize the features of the counter (CTR) operation mode to reduce unnecessary memory copying and operations in the GPU environment. Besides, we optimize the memory usage by making full use of GPU’s on-chip memory such as registers and shared memory and implement the core function of each target algorithm with inline PTX assembly codes for maximizing the performance. With the application of our optimization methods and handcrafted PTX codes, we achieve excellent encryption throughput of 468, 2593, and 3063 Gbps for HIGHT, LEA, and revised CHAM on RTX 2070 NVIDIA GPU, respectively. In addition, we present optimized implementations of Counter Mode Based Deterministic Random Bit Generator (CTR_DRBG), which is one of the widely used deterministic random bit generators to provide a large amount of random data to the connected IoT devices. We apply several optimization techniques for maximizing the performance of CTR_DRBG, and we achieve 52.2, 24.8, and 34.2 times of performance improvement compared with CTR_DRBG implementation on CPU-side when HIGHT-64/128, LEA-128/128, and CHAM-128/128 are used as underlying block cipher algorithm of CTR_DRBG, respectively.

Efficient Implementation of ARX-Based Block Ciphers on 8-Bit AVR Microcontrollers

As the development of Internet of Things (IoT), the data exchanged through the network has significantly increased. To secure the sensitive data with user’s personal information, it is necessary to encrypt the transmitted data. Since resource-constrained wireless devices are typically used for IoT services, it is required to optimize the performance of cryptographic algorithms which are computation-intensive tasks. In this paper, we present efficient implementations of ARX-based Korean Block Ciphers (HIGHT and LEA) with CounTeR (CTR) mode of operation, and CTR_DRBG, one of the most widely used DRBGs (Deterministic Random Bit Generators), on 8-bit AVR Microcontrollers (MCUs). Since 8-bit AVR MCUs are widely used for various types of IoT devices, we select it as the target platform in this paper. We present an efficient implementation of HIGHT and LEA by making full use of the property of CTR mode, where the nonce value is fixed, and only the counter value changes during the encryption. On our implementation, the cost of additional function calls occurred by the generation of look-up table can be reduced. With respect to CTR_DRBG, we identified several parts that do not need to be computed. Thus, precomputing those parts in offline and using them online can result in performance improvements for CTR_DRBG. Furthermore, we applied several optimization techniques by making full use of target devices’ characteristics with AVR assembly codes on 8-bit AVR MCUs. Our proposed table generation way can reduce the cost for building a precomputation table by around 6.7% and 9.1% in the case of LEA and HIGHT, respectively. Proposed implementations of LEA and HIGHT with CTR mode on 8-bit AVR MCUs provide 6.3% and 3.8% of improved performance, compared with the previous best results, respectively. Our implementations are the fastest compared to previous LEA and HIGHT implementations on 8-bit AVR MCUs. In addition, the proposed CTR_DRBG implementations on AVR provide better performance by 37.2% and 8.7% when the underlying block cipher is LEA and HIGHT, respectively.

Copker: A Cryptographic Engine Against Cold-Boot Attacks

Cryptosystems are essential for computer and communication security, e.g., RSA or ECDSA in PGP Email clients and AES in full disk encryption. In practice, the cryptographic keys are loaded and stored in RAM as plain-text, and therefore vulnerable to cold-boot attacks exploiting the remanence effect of RAM chips to directly read memory data. To tackle this problem, we propose Copker , a cryptographic engine that implements asymmetric cryptosystems entirely within the CPU, without storing any plain-text sensitive data in RAM. Copker supports the popular asymmetric cryptosystems (i.e., RSA and ECDSA), and deterministic random bit generators (DRBGs) used in ECDSA signing. In its active mode, Copker stores kilobytes of sensitive data, including the private key, the DRBG seed and intermediate states, only in on-chip CPU caches (and registers). Decryption/signing operations are performed without storing any sensitive information in RAM. In the suspend mode, Copker stores symmetrically-encrypted private keys and DRBG seeds in memory, while employs existing solutions to keep the key-encryption key securely in CPU registers. Hence, Copker releases the system resources in the suspend mode. We implement Copker with the support of multiple private keys. With security analyses and intensive experiments, we demonstrate that Copker provides cryptographic services that are secure against cold-boot attacks and introduce reasonable overhead.

FPGA implementation of SRAM PUFs based cryptographically secure pseudo-random number generator

The security of cryptographic protocols depends on the security of key sequences consisting of random numbers. In this paper, we design a Cryptographically Secure Pseudo-Random Number Generator (CSPRNG), which consists of a hash based Deterministic Random Bit Generator (DRBG) and a Get Entropy module. SRAM Physical Unclonable Functions (PUFs) are regarded as entropy sources, providing entropy data with enough entropy for CSPRNG. The construction of Get Entropy module is proposed to verify the availability of SRAM PUFs and compress the entropy data into truly random seeds that are fed into DRBG. This CSPRNG can reseed itself dynamically and can monitor the entropy of entropy sources in real time. The system is implemented and tested on Altera DE2. The test results show that, the pseudo-random numbers generated by this system can pass all random tests of National Institute of Standards and Technology (NIST) SP800-22 Test Suite and the throughput is up to 598.1 Mbps. Through the security discussion, this CSPRNG is theoretically confirmed that it can be securely applied to cryptographic protocols.

Corrected runs distribution test for pseudorandom number generators

Runs distribution test is an important statistical test based on Golomb's randomness postulates. It is an important randomness test included in some famous evaluation standards and statistical test suites such as Application Notes and Interpretation of the Scheme (AIS20), the Federal Information Processing Standards (FIPS140), CryptX, and so on. However, when it is applied on some well-known good Deterministic Random Bit Generators (DRBGs), the test results show apparent bias from randomness. This shows that there exist some inaccuracies in the runs distribution test. The problem is solved and the runs distribution test through two ways is corrected. First, the degree of freedom of statistical value V is adjusted. Secondly, the expected number of different lengths runs is modified. The experiment results show that the corrected runs distribution test is more accurate under two-level evaluation approach proposed by National Institute of Standards and Technology (NIST) Special Publication (SP) 800–22.

The Importance of Entropy to Information Security

True randomness can't be left to chance. Adopting improved entropy sources that feed into good deterministic random bit generators, together with rigorous estimation of available entropy, will help achieve the guarantees promised by cryptography to protect sensitive information.

Random Key Chaining (RKC): AES Mode of Operation

There is a compelling need for a mode of operation that can efficiently provide authenticated encryption at a higher data rate, and is capable of making use of pipelining and parallel processing. This paper describes Random Key Chaining (RKC) block cipher mode of operation that fills this need. RKC mode makes use of Deterministic Random Bit Generator (DRBG) and with the application of DRBG every block of plaintext is being encrypted with a different key bringing it closer to one-time pad approach. The slight variation of RKC mode can be used as a confidentiality mode that can be used in application like hard-disk compression with reduced computational cost. GENERAL TERMS Security, Authenticated Encryption mode.