Detector Readout Circuits Research Articles

Systematic prediction method for flip-chip bonding connectivity of ultra-large array infrared detector.

The flip-chip bonding technique utilized in ultra-large array infrared detectors has a substantial impact on connectivity rates. The electrical connectivity of the flip-chip bonding process exhibits randomness due to the difficulties in the surface control of large-scale devices. This restriction hinders the development of ultra-large array devices. In this work, the surface shape matching calculation is performed based on the surface shape distributions measured from infrared detector chips and readout circuits. The multi combinations and multi rotation angles are employed to calculate the distribution of combined surface distances, and the combined PV (peak-to-valley) value is applied to describe the severity of surface mismatch. Test devices with combined PV values ranging from 7.460 µm to 4.265 µm are prepared and tested, and the connectivity rate achieves an improvement from 74.57% to 99.75% between mismatched devices and matching devices. The electrical test results of test devices indicate that disconnections tend to cluster in areas where surface distance is over 5 µm, which is determined by extracting and analyzing the surface distance correlated to electrical test results. A standard based on the combined PV value is established to select matching combinations and ensure a high connectivity rate of 99% or 97% for infrared detectors, while the connectivity rates of randomly selected devices are no higher than 91%. This work presents a systematic method to predict and improve the connectivity rate of flip-chip bonding process for ultra-large array infrared detector.

Low-noise fast-response readout circuit to improve coincidence time resolution

Time-of-flight (TOF) PET detectors with fast-rise-time scintillators and fast-single photon time resolution silicon photomultiplier (SiPM) have been developed to improve the coincidence timing resolution (CTR) to sub-100 ps. The CTR can be further improved with an optimal bandwidth and minimized electronic noise in the readout circuit and this helps reduce the distortion of the fast signals generated from the TOF-PET detector. The purpose of this study was to develop an ultra-high frequency and fully-differential (UF-FD) readout circuit that minimizes distortion in the fast signals produced using TOF-PET detectors, and suppresses the impact of the electronic noise generated from the detector and front-end readout circuits. The proposed UF-FD readout circuit is composed of two differential amplifiers (time) and a current feedback operational amplifier (energy). The ultra-high frequency differential (7 GHz) amplifiers can reduce the common ground noise in the fully-differential mode and minimize the distortion in the fast signal. The CTR and energy resolution were measured to evaluate the performance of the UF-FD readout circuit. These results were compared with those obtained from a high-frequency and single ended readout circuit. The experiment results indicated that the UF-FD readout circuit proposed in this study could substantially improve the best achievable CTR of TOF-PET detectors.

Fully Integrated Line Array Angular Displacement Sensing Chip

The angular displacement sensor is a digital angular displacement measurement device that integrates optics, mechanics, and electronics. It has important applications in communication, servo control, aerospace, and other fields. Although conventional angular displacement sensors can achieve extremely high measurement accuracy and resolution, they cannot be integrated because complex signal processing circuitry is required at the photoelectric receiver, which limits their suitability for robotics and automotive applications. The design of a fully integrated line array angular displacement-sensing chip is presented for the first time using a combination of pseudo-random and incremental code channel designs. Based on the charge redistribution principle, a fully differential 12-bit, 1 MSPS sampling rate successive approximation analog-to-digital converter (SAR ADC) is designed for quantization and subdivision of the incremental code channel output signal. The design is verified with a 0.35 μm CMOS process and the area of the overall system is 3.5 × 1.8 mm2. The fully integrated design of the detector array and readout circuit is realized for the angular displacement sensing.

Performance of the polarization leakage correction in the PILOT data

The Polarized Instrument for Long-wavelength Observation of the Tenuous interstellar medium (PILOT) is a balloon-borne experiment that aims to measure the polarized emission of thermal dust at a wavelength of 240 um (1.2 THz). The PILOT experiment flew from Timmins, Ontario, Canada in 2015 and 2019 and from Alice Springs, Australia in April 2017. The in-flight performance of the instrument during the second flight was described in Mangilli et al. 2019. In this paper, we present data processing steps that were not presented in Mangilli et al. 2019 and that we have recently implemented to correct for several remaining instrumental effects. The additional data processing concerns corrections related to detector cross-talk and readout circuit memory effects, and leakage from total intensity to polarization. We illustrate the above effects and the performance of our corrections using data obtained during the third flight of PILOT, but the methods used to assess the impact of these effects on the final science-ready data, and our strategies for correcting them will be applied to all PILOT data. We show that the above corrections, and in particular that for the intensity to polarization leakage, which is most critical for accurate polarization measurements with PILOT, are accurate to better than 0.4 % as measured on Jupiter during flight#3.

Development of series SQUID array with on-chip filter for TES detector

A cold preamplifier based on superconducting quantum interference devices (SQUIDs) is currently the preferred readout technology for the low-noise transition edge sensor (TES). In this work, we have designed and fabricated a series SQUID array (SSA) amplifier for the TES detector readout circuit. In this SSA amplifier, each SQUID cell is composed of a first-order gradiometer formed using two equally large square washers, and an on-chip low pass filter (LPF) as a radio-frequency (RF) choke has been developed to reduce the Josephson oscillation interference between individual SQUID cells. In addition, a highly symmetric layout has been designed carefully to provide a fully consistent embedded electromagnetic environment and achieve coherent flux operation. The measured results show smooth V–Φ characteristics and a swing voltage that increases linearly with increasing SQUID cell number N. A white flux noise level as low as 0.28 μ Φ 0/Hz1/2 is achieved at 0.1 K, corresponding to a low current noise level of 7 pA/Hz1/2. We analyze the measured noise contribution at mK-scale temperatures and find that the dominant noise derives from a combination of the SSA intrinsic noise and the equivalent current noise of the room temperature electronics.

Characterization of the STS/MUCH-XYTER2, a 128-channel time and amplitude measurement IC for gas and silicon microstrip sensors

New physics experiments at the Facility for Antiproton and Ion Research (FAIR) in Darmstadt require application-optimized detector readout circuits. The STS/MUCH-XYTER2 (or SMX2) is a new, 128-channel prototype ASIC for silicon strip detectors and gas electron multiplier (GEM) detectors in the Compressed Baryonic Matter (CBM) experiment. It provides self-triggered amplitude and time measurement of incoming charge and serial streaming of digitized data. The 10 mm × 6.75 mm chip was fabricated employing the UMC CMOS 180 nm process. It comprises of an analog front-end with dual-path processing including a timing comparator in one path and a continuous-time 5-bit analog-to-digital converter in the other path, a digital back-end with time pre-sorting, advanced monitoring and throttling features and multiple 320 Mbps, serial links targeted for a GBT-based data acquisition structure. Specific conditions of the detector systems will be discussed prior to the structure and the features of the ASIC together with measurement results.

GaN基紫外探测器读出电路注入效率

GaN基紫外探测器读出电路注入效率

An Effective Multilevel Offset Correction Technique for Single Photon Counting Pixel Detectors

We report on a novel technique of an in-pixel multilevel offset correction to be used in hybrid pixel detector readout circuits operating in a single photon counting mode. This technique was implemented in a prototype integrated circuit consisting of 23,552 square shaped pixels of 75 μm pitch, which was designed and manufactured in CMOS 130 nm technology. Each pixel contains a charge sensitive amplifier, shaper, two discriminators, two 14-bit counters and a block for multilevel offset correction. The effective gain and offset are controlled individually in each pixel. The measurement results prove very good uniformity of the prototype integrated circuit with an offset spread of only 7e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> rms and a gain spread of 2.5%.

Pulse shape distortion of output signals from single-crystal CVD diamond detector in few-GHz broadband amplifiers

The response of a diamond detector made from a single crystal grown by chemical vapour deposition was studied using a broadband amplifier. A short pulse width of for 241Am-α-particles was observed with a digital oscilloscope. To discuss pulse shape distortion from the detector in a measurement system, we simulated waveforms with a SPICE simulator using an equivalent circuit model that contained three main parts: detector, amplifier, and oscilloscope. In the simulation, we found that the pulse width spread by more than 200 ps following amplification. We discuss the effects of the detector read-out circuit time constant on the observed waveforms and confirm that the pulse width spread was restrained by use of a short time constant compared with carrier drift time in diamond crystals.

Optimization of Single Flux Quantum Circuit Based Comparators Using PSO

In the recent years, a number of groups have shown that 1-bit comparators are suitable candidates for a number of circuits such as front-end of the low temperature detector readout circuits and analog to digital converters. Even though a number of tools exist for the development of digital logic gates, we are not aware of any optimizer for analog circuits that takes into account the stochastic effects in the Josephson junctions. Comparator circuits contain just a few parameters and have been analyzed extensively by a number of groups for over a decade. However, designing the comparator cells by hand is tedious work since it is based on the statistical analysis of the input–output relations of the cell. For the result to be reliable enough, statistically meaningful number of input SFQ pulses should be generated and corresponding output pulses should be analyzed. In addition, the design parameters should be suitable for fabrication and compatible for the rest of the cell library.

Ultralow-Dark-Current CdHgTe FPAs in the SWIR Range at CEA and Sofradir

We report the first results of work carried out at CEA and Sofradir to build ultralow-dark-current focal-plane arrays (FPAs) in the short-wave infrared range (SWIR) for space applications. These FPAs are designed to detect very low flux in the 2-μm wavelength range. To this end, Sofradir has designed a source follower per detector read-out circuit (ROIC, 384 × 288, 15 μm pitch). This ROIC has been hybridized on different HgCdTe diode configurations processed at CEA-LETI, and low-flux characterizations have been carried out at CEA-IRFU at low temperature (from 60 K to 160 K). Both ion-implanted p/n and n/p diodes have been evaluated. The metallurgical nature of the absorbing layer has also been examined, and both molecular-beam epitaxy (MBE) and liquid-phase epitaxy (LPE) have been applied. Dark-current measurements are discussed in comparison with previous results from the literature. State-of-the-art dark currents are recorded for temperatures higher than 120 K. At temperatures lower than 100 K, the decrease in dark current flattens out for both technologies. In this region, currents between 0.4 e–/s/pixel and 0.06 e–/s/pixel are reported.

Design and Circuit Analysis of Quasi-one Junction SQUID Comparators for Low Temperature Detector Array Read-out

In this study, we report on our simulation and experimental results for quasi-one junction SQUIDs (QOS) comparator targeted to be used in the front-end of the detector read-out circuits. The QOS is used as a 1-bit quantizer in the front-end of the read-out circuit. Their performance and reliability is very much depending on the circuit parameters of the QOSs. The main design parameters are the threshold level, gray zone width, and the chip-to-chip reproducibility over different fabrication batches. For some special applications, such as detector readout, the overall power consumption needs to be sufficient small. We measured threshold and gray zone counting each individual switching event for various bias and input current values and for different QOS designs. In addition, circuit simulations including thermal noise are used to explain the observed circuit behavior and to optimize design parameters.

Improvements in Operating the Raytheon 320 × 240 Pixel Si:As Impurity Band Conduction Mid‐Infrared Array

ABSTRACTWe have developed a new operating method for the Raytheon 320 × 240 pixel Si:As IBC detector (hereafter 320 × 240 FPA), the largest mid‐infrared array detector currently available designed for ground‐based astronomy. The array shows quite a strange behavior when a bright source is observed. In images that contain a stellar object sufficiently brighter than the background flux, the signal level of the 320 × 240 FPA drops in the vicinity or along the same row or column of the stellar object. The level‐drop phenomena are caused mainly by transient variations in the characteristics of the source followers in the detector readout circuit (ROIC). We successfully corrected the variations by correlated quadruple sampling, which reduces the level‐drop phenomena appreciably. We evaluated the properties of the ROIC and optimized the bias voltages supplied for the array. The detective quantum efficiency of the 320 × 240 FPA was also estimated.

Noise analysis in linear electronic circuits

Abstract Despite extensive literature on the analysis of noise in electronic circuits [1–7], it is sometimes difficult to generate an understanding at a useful fundamental level. The plethora of symbols used for a variable in different analysis can also make it very difficult to keep track of the exact units used and factors of 2 and 2π can be easily misplaced. The analysis that follows will develop some useful equations from plausible noise sources in a short argument. The emphasis is to minimise the mathematical path in order to keep an eye on the dimensions and constants. It is hoped that this paper can pull enough of the relevant arguments together at one time to provide a useful overview. While this analysis is of general use in linear electronic circuits, the initial motivation for the work was to analyse radiation detector systems. The text contains examples of detector readout circuits which demonstrate the use of the equations developed.

DMILL, a mixed analog-digital radiation-hard BICMOS technology for high energy physics electronics

High Energy Physics experiments under preparation at CERN (Geneva, Switzerland) with the future LHC (Large Hadron collider) require a fast, low noise, very rad-hard, mixed analog-digital microelectronics VLSI technology. Readout electronics designed using such a technology for the central parts of the LHC particle detectors must withstand more than 10 Mrad (SiO/sub 2/) and 10/sup 14/ neutrons/cm/sup 2/ over 10 years of operation. We present here recent results obtained with a new rad-hard analog-digital technology called DMILL, which monolithically integrates NPN bipolar, CMOS and P-JFET transistors, and which has been specifically developed to fulfill the severe constraints of LHC detector readout circuits.

Theoretical evaluation of InTIP, InTIAs, and InTISb As longwave infrared detectors

We have evaluated three III-V semiconductor alloys—In1−xTlxP (ITP), In1−xTlxAs (ITA), and In1−xTlxSb (ITS)—as possible candidates for future long-wave infrared (LWIR) detector materials. The cohesive energies, elastic constants, band structures, electron mobilities, and phase diagrams are calculated and are compared to those of Hg1−xCdxTe (MCT) alloys. The band gaps of all three III-V alloys change from negative to positive values as the alloy composition x decreases from 1 to 0. The x values for the 0.1-eV gap are estimated to be 0.67, 0.15, and 0.08, respectively, for ITP, ITA, and ITS. While both ITP and ITA form stable zincblende solid solutions for all alloy compositions, zincblende ITS is stable only for a range of x less than 0.15. The complication of the phase diagram in ITS is caused by the existence of a stable CsCl phase for pure TISb. The alloy mixing enthalpies for ITP and ITA are comparable to those in MCT, and their phase diagrams should be qualitatively similar, characterized by simple lensshape liquidus and solidus curves. Both ITP and ITA have considerably larger cohesive energies and elastic constants than those of MCT, indicating that they are structurally robust. At a 0.1-eV gap, the band structures near the gap and the electron mobilities in ITP, ITA, and ITS are also found to be comparable to those of MCT. Since the lattice constants of TIP and TIAs are less than 2% larger than the respective values in InP and InAs, the latter should provide natural substrates for the growth of active LWIR alloys and offer a potential to integrate the detector array and read-out circuit.

The GLUEchip: a custom VLSI chip for detector readout and associative memories circuits

An associative memory full-custom VLSI chip for pattern recognition has previously been designed and tested. It is the AMchip, and contains 128 patterns of 60 bits each. To expand the pattern capacity of an associative memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips; the resulting treelike structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor of 16 for each GLUEchip used.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>