Abstract

We report on a novel technique of an in-pixel multilevel offset correction to be used in hybrid pixel detector readout circuits operating in a single photon counting mode. This technique was implemented in a prototype integrated circuit consisting of 23,552 square shaped pixels of 75 μm pitch, which was designed and manufactured in CMOS 130 nm technology. Each pixel contains a charge sensitive amplifier, shaper, two discriminators, two 14-bit counters and a block for multilevel offset correction. The effective gain and offset are controlled individually in each pixel. The measurement results prove very good uniformity of the prototype integrated circuit with an offset spread of only 7e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> rms and a gain spread of 2.5%.

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