Detection Of Permanent Faults Research Articles

Permanent fault identification and location scheme for MTDC grid based on equivalent impedance phase characteristics and distributed parameter line

To ensure the reliability of the MTDC grid's recovery system during the reclosing stage, identifying permanent faults is crucial. Therefore, a permanent fault identification and location scheme is proposed based on equivalent impedance phase characteristics and distributed parameter lines. The equivalent impedances with distributed parameter lines in permanent and temporary faults are investigated. The proposed scheme for identifying a permanent fault is based on the phase characteristics of the equivalent impedances. The proposed scheme for permanent fault location is achieved by solving the fault location equation considering distributed parameter lines to determine the fault distance. Simulation results indicate that the proposed scheme is suitable for long-distance DC transmission lines and is less affected by the sampling rate, fault locations, fault resistance, and noise. The proposed scheme improves the reliability and sensitivity of permanent fault detection.

Learning-based reliability assessment method for detection of permanent faults in clockless circuits

Permanent faults are a common issue of contemporary CMOS circuits during fabrication and its lifetime. In order to detect these faults, designers adopt logic and delay-oriented testing approaches to validate the circuit's structure. However, for clockless (i.e. asynchronous) circuits, applying well-known testing approaches is not trivial and bring undesirable overheads. To overcome that, the proposed method in this paper leverages the current signature properties of asynchronous circuits to detect permanent resistive-based faults. Through simulation experiments, we show the natural ability of asynchronous circuits in providing useful current signatures for identifying the presence of resistive-based faults. Moreover, the results demonstrate that our testing technique requires no extra circuitry or power ports to detect resistive-short faults ≤ 3kΩ and resistive-open faults ≥ 70kΩ.

Intermittent Fault Detection with T2 Control Chart

Multivariate statistical analysis using the Hotellings T2 statistic (T2 control chart) is one of the most effective data-driven methods for fault detection. However, existing T2 control charts in the literature mainly focus on permanent faults, and intermittent faults are relatively rarely considered. In fact, due to the small magnitude and short duration characteristics, traditional multivariate statistical methods are not sensitive to intermittent faults, resulting in much missed detection. Thus in this paper, the T2 control chart with consecutive observations is designed for permanent fault detection and intermittent fault detection respectively. In order to analyze the detection ability of proposed methods, definitions of being guaranteed detectable are introduced both for permanent faults and intermittent faults. Then, sufficient conditions for the defined fault detectability are derived for both kinds of faults respectively. Moreover, optimal window length for intermittent fault detection is discussed. Finally a simulation study is carried out to show the effectiveness of the proposed methods.

Stochastic testing of processing cores in a many-core architecture

A promising solution to reliability challenges in nano-scale fabrication technologies is self-test and reconfiguration. In this direction, we propose an autonomous test mechanism for online detection of permanent faults in many-core processors. Several hardware test components are incorporated in the many-core architecture. Some of these components distribute software-based self-test routines among the processing cores and make each test routine accessible for a limited amount of time. A processing core that has an idle slot executes the test routine, otherwise it skips it without loss of test continuity. Several components of the proposed test architecture monitor behavior of the processing cores during execution of test routines, detect faulty cores, and make their omission from the system possible. We propose the use of an extended form of Petri NET modeling method to model and analyze the proposed test mechanism and tune our test architecture to preserve quality of test, and at the same time, manage the overall test time. Our experimental results show that test time and hardware overhead of the proposed test mechanism are low and its performance overhead is zero. Furthermore, the proposed test architecture can efficiently scale to a many-core with a large number of processing cores.

Analysis of current and voltage indicators in grid connected PV (photovoltaic) systems working in faulty and partial shading conditions

To ensure the optimization of the energy generated by grid connected PV (photovoltaic) systems is necessary to plan a strategy of automatic fault detection. The analysis of current and voltage indicators have demonstrated effectiveness in the detection of permanent faults in the PV array in real time as short-circuits or open circuits present in the system. In this paper, the analysis of the evolution of these indicators is focused on the detection of temporary faults due to partial shade on the PV array or disconnection of the inverter in case of grid fluctuations of voltage or frequency to prevent islanding. These situations can be identified by observation of the evolution of both indicators and power losses due to these effects can be evaluated from them. The analysis and experimental validation were carried out in two grid connected PV systems in Spain and Algeria.

Identificación y localización de fallas en sistemas de distribución, utilizando medidores de calidad del servicio de energía eléctrica

Este artículo presenta una nueva metodología para la identificación y localización de fallas en sistemas de distribución de energía eléctrica, por medio de la implementación de medidores electrónicos que registren la continuidad en el servicio eléctrico. La implementación de los registradores, facilita detectar fallas permanentes o transitorias en redes no homogéneas, proporcionando información sobre puntos débiles de los sistemas de potencia, para luego poder adoptar medidas correctivas con respecto a la duración y frecuencia de las interrupciones, en los circuitos de los sistemas de distribución local. A través de este mecanismo de regulación de los sistemas desde la generación, comercialización, distribución y operación de la electricidad, se plantea una solución que permita mitigar la discontinuidad del servicio y los cuantiosos costos que producen a los agentes del sector eléctrico y, principalmente, a los usuarios de la energía eléctrica.

A Comparative Evaluation of Designs for Reliable Memory Systems

This paper addresses the design of storage systems for operation under critical environmental conditions. For these applications, these systems should have low latency time in access, high performance in throughput and high storage capabilities; therefore, they must be assembled using highly reliable components, while allowing flexibility in design. Commercial Off The Shelf (COTS) components have often been used. A COTS-based architecture is analyzed in this paper; the proposed architecture uses design-level techniques (such as error detection/correction codes and scrubbing) to make commercially available Dynamic Random Access Memory (DRAM) chips tolerant to faults. This paper provides a complete and novel analysis of engineering alternatives which arise in the design of a highly reliable memory system based on Reed Solomon coding. A comparative analysis of methods for permanent fault detection is provided; moreover using a Markovian characterization, different functional arrangements (based on code and scrubbing frequency) are investigated and evaluated.

Test for detection and location of intermittent faults in combinational circuits

Faults in combinational circuits are either permanent or intermittent. Intermittent faults tend to be environment-dependent; hence altering the environment might rectify these faults. These faults can be detected by applying random input-vectors (IV). The existence of random intermittent faults might require applying more random IV before detection. The detection of permanent faults requires fewer random IV but correction demands location and replacement of the faulty device, if repair is not feasible. Thus correction of a permanent fault costs more than that of an intermittent fault. The correction cost can be reduced by detecting the type of fault. Since most operational failures in a circuit are due to intermittent faults, it is very important to detect the type of fault in order to find a cheaper solution. This paper discusses the behavior of permanent and intermittent faults in combinational circuits, and introduces a test-detection model (TDM) for these faults. The error latency for an intermittent fault is derived. Two test-strategies are intermixed in the model: random testing for fault-detection, and deterministic testing for deciding on the type of fault. The activity of intermittent faults that requires the minimum number of IV for detection is emphasized. Simulation is used to demonstrate the validity of TDM. Although the variables required in TDM can be difficult to evaluate, estimation of their values is not impossible. A worst-case analysis can always be adopted, where variables are easily evaluated, to find an upper bound on the error latency; thus detection of an intermittent fault is assured with a very high probability. The cost-saving offered by intermittent-fault corrections shows the practical aspect of TDM.

On testing of sequential machines using circuit decomposition and stochastic modeling

Test generation for sequential circuits has been a difficult task. This is due to the large search space to be considered in test pattern generation. In this paper the detection of permanent faults in sequential circuits by random testing is analyzed utilizing the circuit partitioning approach together with a continuous parameter Markov model. Given a large sequential circuit, it is partitioned into several smaller partitions using either series or parallel decomposition. For each partition with certain stuck faults specified, the original state table and its error version are derived from an analysis of the partition under fault-free and faulty conditions, respectively. A random testing strategy that uses a three-state Markov model is used for detecting permanent stuck faults. Experimentation on various sequential circuits has shown that a significant saving in testing or test generation time can be achieved if we partition the circuit and then test each of its components as opposed to testing the circuit in its original form. >

Toward a definition of fault analysis for petri nets models

We introduce a particular kind of Petri net, restricted Petri nets (RPN), along with a set of definitions and theoretical results which enable RPN to be use in fault detection processes. A fault for an arbitrary system is interpreted in terms of a faulty transition in an RPN. This paper focuses on the detection of permanent faults in a transition which occur because of the absence of some input arcs (or output arcs) from its fault-free structure.

An efficient strategy for the detection of faults and a domino-free recovery in distributed systems

The increasing researches and proposals of multiprocessors and distributed systems have focused the interest of several research groups on an integrated approach to the problem of fault tolerance in its multifold aspects. The approach followed in this paper for the detection of faults and the recovery of the system is based on an environment of cooperating processes which communicate with each other by means of explicit asynchronous communication. The main assumptions on which the work is carried out are: 1. i) there are no software bugs, 2. ii) the system is provided with some mechanism for the implementation of stable memory. The proposed policy deals, in an integrated way, with transient faults as well as permanent ones. It is worthwhile to point out that transient faults are detected by means of special tests inserted in the processes independently by each other. The recovery policy is backward, it is based on dynamic individuation of a minimal recovery line performed by the kernel of the operating system. That policy is domino effect free and does not impose synchronization among the processes. The embedding on this scheme of a distributed diagnosis procedure, allows the detection of permanent faults and the recovery of the system.

Functional Testing of Semiconductor Random Access Memories

This paper presents an overview of the problem of testing semiconductor random access memories (RAMs). An important aspect of this test procedure is the detection of permanent faults that cause the memory to function incorrectly. Functional-level fault models are very useful for describing a wide variety of RAM faults. Several fault models are &scussed throughout the paper, including the stuck-at-0/1 faults, coupled-cell faults, and single-cell pattern-sensitive faults. Test procedures for these fault models are presented and their fault coverage and execution times are discussed. The paper is intended for the general computer scmnce audience and presupposes no background in the hardware testing area.

Minimal Fault Tests for Redundant Combinational Networks

This correspondence is concerned with the detection of permanent faults in redundant combinational networks. Fault masking in such networks is examined. A method for determining an optimal test set that will detect all detectable faults is given.