Detection Of Design Errors Research Articles

Comparative Effectiveness of Mixed Reality-Based Virtual Environments in Collaborative Design

This paper presents two mixed-reality (MR) environments that provide alternative mediums that allow groups of people to share the same work and communication space in face-to-face and remote manners. Two experiments were executed to test the capabilities of the two MR systems in realistic environment and collaborative tasks against prevalent methods. Results indicated that the two MR systems significantly reduced the performance time for the collaborative design error detection task. Results also indicated less mental effort for the MR systems, suggesting that some of the mental interpretation for the error detection task is offloaded to the MR systems.

An evaluation of timed scenario notations

There is a general consensus on the importance of good Requirements Engineering (RE) for achieving high quality software. The modeling and analysis of requirements have been the main challenges during the development of complex systems. Although semi-formal, scenario driven approaches have raised the awareness and use of requirement engineering techniques, mostly because of their intuitive representation. Scenarios are a well established approach to describe functional requirements, uncovering hidden requirements and trade-offs, as well as validating and verifying requirements. The ability to perform quantitative analysis at the requirements level supports the detection of design errors during the early stages of a software development life cycle, and helps reduce the cost of later redesign activities. In order to achieve this goal, non-functional aspects and in particular time-related aspects have to be incorporated at the software requirement phase. This is essential in order to correctly model and analyze time dependent applications at early stages in system development. The widespread interest in time modeling and analysis techniques provides the major motivation for our paper. The objective of the article is to provide readers with sufficient knowledge about existing timed scenario approaches to guide them in making informed decisions to when and how time aspects can be incorporated in their development process. In order to support this process, we present a comprehensive classification, evaluation and comparison of time-based scenario notations. In order to evaluate these existing notations, we introduce a set of eleven time-related criteria and apply them to categorize and compare forty seven scenario construction approaches.

Use of a lightweight formal method to model the static aspects of state machines

In this paper the author uses Alloy as a modeling language to model the elements that form a state machine and the rules that govern how they can be connected. In particular, the model proposed in this paper focuses in the static aspects of state machines. To analyze and detect design errors in the model, the Alloy analyzer was used. With the use of this tool, design errors can be detected very quickly. This tool can also generate instances of the model without making a line of code. The paper presents two models based on the formal approach: a graphical model and a textual model. The graphical model is used as an overview of the system while the textual model is used to establish further constraints on the graphical model.

A Control-Oriented Coverage Metric and its Evaluation for Hardware Designs

Problem statement: Dynamic verification, the use of simulation to determine design correctness, is widely used due to its tractability for large hardware designs. A serious limitation of dynamic techniques is the difficulty in determining whether or not a test sequence is sufficient to detect all likely design errors. Coverage metrics are used to address this problem by providing a set of goals to be achieved during the simulation process; if all coverage goals are satisfied then the test sequence is assumed to be complete. Coverage metrics hence evaluate the ability of a test sequence to detect design errors and are essential to the verification process. A key source of difficulty in determining error detection is that the control-flow path traversed in the presence of an error cannot be determined. This problem becomes particularly difficult in case of typical industrial designs involving interaction of control flow paths between concurrent processes. Error detection can only be accurately determined by exploring the set of all control-flow paths, which may be traversed as a result of an error. Also, there is no technique to identify a correlation between coverage metrics and hardware design quality. Approach: We present a coverage metric that determined the propagation of error effects along all possible erroneous control-flow paths across processes. The complexity of exploring multiple control-flow paths was greatly alleviated by heuristically pruning infeasible control-flow paths using the algorithm that we present. We also presented a technique to evaluate coverage metric by examining its ability to ensure the detection of real design errors. We injected errors in the design to correlate their detection with the coverage computed by our metric. Results: Our coverage metric although analyzed all control-flow paths it pruned the infeasible ones and eliminated them from coverage consideration, hence reducing the complexity of generating tests meant to execute them. The metric also correlated better with detection of design errors than some well-studied metrics do. Conclusion: The proposed coverage metric provided high accuracy in measurement of coverage in designs that contain complex control-flow with concurrent processes. It is superior at detecting design error when compared with the metrics it was compared with.

Constrained types for object-oriented languages

X10 is a modern object-oriented language designed for productivity and performance in concurrent and distributed systems. In this setting, dependent types offer significant opportunities for detecting design errors statically, documenting design decisions, eliminating costly run-time checks (e.g., for array bounds, null values), and improving the quality of generated code. We present the design and implementation of constrained types , a natural, simple, clean, and expressive extension to object-oriented programming: A type C{c} names a class or interface C and a constraint c on the immutable state of C and in-scope final variables. Constraints may also be associated with class definitions (representing class invariants) and with method and constructor definitions (representing preconditions). Dynamic casting is permitted. The system is parametric on the underlying constraint system: the compiler supports a simple equality-based constraint system but, in addition, supports extension with new constraint systems using compiler plugins.

VERIFICATION OF DATAFLOW SCHEDULING

This paper presents the formal verification method for high-level synthesis (HLS) to detect design errors of dataflow algorithms by using Petri Net (PN) and symbolic-model-verifier (SMV) techniques. Formal verification in high-level design means architecture verification, which is different from functional verification in register transfer level (RTL). Generally, dataflow algorithms need algorithmic transformations to achieve optimal goals and also need design scheduling to allocate processor resources before mapping on a silicon. However, algorithmic transformations and design scheduling are error-prone. In order to detect high-level faults, high-level verification is applied to verify the synthesis results in HLS. Instead of applying Boolean algebra in traditional verification, this paper adopts both Petri Net theory and SMV model checker to verify the correctness of the synthesis results of the high-level dataflow designs. In the proposed hybrid verification method, a high-level design or DUV (design-under-verification) is first transformed into a Petri Net model. Then, Petri Net theory is applied to check the correctness of its algorithmic transformations of HLS, and the SMV model checker is used to verify the correctness of the design scheduling. We presented two approaches to realize the proposed verification method and concluded the best one who outperforms the other in terms of processing speed and resource usage.

What causes a system to satisfy a specification?

Even when a system is proven to be correct with respect to a specification, there is still a question of how complete the specification is, and whether it really covers all the behaviors of the system.Coverage metricsattempt to check which parts of a system are actually relevant for the verification process to succeed. Recent work on coverage in model checking suggests several coverage metrics and algorithms for finding parts of the system that are not covered by the specification. The work has already proven to be effective in practice, detecting design errors that escape early verification efforts in industrial settings. In this article, we relate a formal definition of causality given by Halpern and Pearl to coverage. We show that it gives significant insight into unresolved issues regarding the definition of coverage and leads to potentially useful extensions of coverage. In particular, we introduce the notion ofresponsibility, which assigns to components of a system a quantitative measure of their relevance to the satisfaction of the specification.

Diagnosis and Consulting for Control Network Performance Engineering of CSMA-Based Networks

Network performance engineering can verify the design and dimensioning of large-scale control networks like CSMA-based building automation networks. It combines performance analysis with diagnosis methods to evaluate the network utilization and to detect design errors before installation and can therewith save the expenses of overdimensioning and redesign. This paper will develop a diagnosis model based on fault trees that is able to use the huge amount of performance analysis results to identify design errors and analyze their coherences. This enables not only a fast tracing back of fault causes and the derivation of solutions; it can also visualize the fault coherence to the user and help him to understand his design. Additional consulting tools implement best practice strategies, to support the user in parameterization.

User perspectives on mixed reality tabletop visualization for face-to-face collaborative design review

Mixed Reality (MR) technologies create an environment where virtual objects and real objects can be presented together on a single display. An MR-based face-to-face design review prototype was created for the purpose of improving design review collaboration. The work presented in this paper investigated how users experienced virtual models in the MR system and assessed the users' experience and attitude towards the effectiveness of the MR tool for design review as compared with a 3D paper-based method. The findings from user feedback suggest that the MR tool may facilitate problem-solving and the quantity of work in a given amount of time and that virtual design displayed in the mixed scene was a useful aid in the design error detection task. Experimental usability evaluation of the MR system was also implemented and suggestions for improvements of the human–computer interface of future system versions were produced.

Verification method of dataflow algorithms in high-level synthesis

This paper presents a formal verification algorithm using the Petri Net theory to detect design errors for high-level synthesis of dataflow algorithms. Typically, given a dataflow algorithm and a set of architectural constraints, the high-level synthesis performs algorithmic transformation and produces the optimal scheduling. How to verify the correctness of high-level synthesis becomes a key issue before mapping the synthesis results onto a silicon. Many tools exist for RTL (Register Transfer Level) design, but few for high-level synthesis. Instead of applying Boolean algebra, this paper adopts the Petri Net theory to verify the correctness of the synthesis result, because the Petri Net model has the nature of dataflow algorithms. Herein, we propose three approaches to realize the Petri Net based formal verification algorithm and conclude the best one who outperforms the others in terms of processing speed and resource usage.

Model Checking Rational Agents

Agent-oriented programming techniques seem appropriate for developing systems that operate in complex, dynamic, and unpredictable environments. We aim to address this requirement by developing model-checking techniques for the (automatic or semiautomatic) verification of rational-agent systems written in a logic-based agent-oriented programming language. Typically, developers apply model-checking techniques to abstract models of a system rather than the system implementation. Although this is important for detecting design errors at an early stage, developers might still introduce errors during coding. In contrast, developers can directly apply our model-checking techniques to systems implemented in an agent-oriented programming language, automatically verifying agent systems without the usual gap between design and implementation. We developed our techniques for AgentSpeak, a rational-agent programming language based on the AgentSpeak (L) abstract agent-oriented programming language. AgentSpeak shares many features of the agent-oriented programming paradigm. Similarly, we've developed techniques for automatically translating AgentSpeak programs into the model specification language of existing model-checking systems. In this way, we reduce the problem of verifying that an AgentSpeak system has certain BDI logic properties to a conventional LTL model-checking problem.

Semiautomated Detection of Design Errors in 2D Drawings Using 3D Reconstruction

Abstract: This article reports an extension of a previous study on developing a systematic approach to construction rework diagnosis and reduction (Li and Love, 1998; Love, Li, and Mandal, 1998a,b; Love, Smith, and Li, 1998). Existing studies identified that design errors are a primary source (cause) of rework in construction, contributing to 51% of the total failure costs of rework (Li and Love, 1998; Hammarlund and Josephson, 1991). Among these design errors, most of them are attributable to dimensional inconsistencies presented in different sets or sections of engineering drawings (Mondal et al., 2000). In this article, we present a set of virtual reality (VR) enabled 3D reconstruction and collision‐detection techniques to automatically identify and minimize design errors. The 3D reconstruction technique can reconstruct 3D models from three 2D orthographic views. This process helps identify many dimensional inconsistencies within different orthographic views of the same object that give rise to incomplete/irregular 3D models. The 3D reconstruction technique is based on the algorithm developed in Wang et al. (2001) for automatic reconstruction of 3D models from three 2D orthographic views. The 3D models provide input to the collision detection study for identifying inter‐object dimensional inconsistencies. Thus, the integrated application of 3D reconstruction and the collision‐detection techniques is able to identify all the dimensional inconsistencies within and between objects. In this article, the 3D reconstruction technique and the collision detection technique are described through their applications in handling construction drawings.

Hierarchical Testability Assisted Intelligent Simulation

Recognizing different hierarchy types permits one to comprehensively constructively use them, to structurally symbolically object-oriented represent them, and to combine them for self-organization towards conscience. Knowledge and construction hierarchies enable the integration of design and analysis into simulation; symbolized object-oriented concepts can formally handle data and operations; structural representation of behaviour manages its realization. Testability at higher simulation levels helps intelligent simulation, as sincerity assists intelligence comprehension. Testing is an important issue, but most research is concentrated at low abstraction levels of the simulation. The objective of testing, to ensure fault-free hardware⁄ software or hard-soft systems, is performed on final constructs, to detect physical faults introduced during/after production, whereas verification aims at detection of design errors. A modern design flow contains high-level synthesis that transforms behavioural specification in a formal one, for example, register-transfer logic, further synthesized to production specification by a compiler.

Pattern-based verification of connections to intellectual property cores

Verification of designs containing pre-designed cores is a challenging topic in modern IC design, since traditional approaches generally do not use the information that parts of the design (like IP cores) are already verified. The port order fault model (POF) has recently been introduced for detecting design errors occurring during integration of a core into a system-on-chip or during test logic insertion. In this work, we generate verification patterns with 100% coverage of a sub-class of POF, called 2-POF. We provide theoretical arguments and experimental results backing the efficiency of these patterns also for detecting higher-order POFs. Moreover, verification pattern sets generated by our approach are more compact compared to the results published before.

Polynomial Formal Verification of Multipliers

Not long ago, completely automatical formal verification of multipliers was not feasible, even for small input word sizes. However, with Multiplicative Binary Moment Diagrams (aBMD), which is a new data structure for representing arithmetic functions over Boolean variables, methods were proposed by which verification of multipliers with input word sizes of up to 256 Bits is now feasible. Unfortunately, only experimental data has been provided for these verification methods until now. In this paper, we give a formal proof that logic verification with aBMDs is polynomially bounded in both, space and time, when applied to the class of Wallace-tree like multipliers. Using this knowledge online detection of design errors becomes feasible during a verification run.

Formal verification of human-automation interaction.

This paper discusses a formal and rigorous approach to the analysis of operator interaction with machines. It addresses the acute problem of detecting design errors in human-machine interaction and focuses on verifying the correctness of the interaction in complex and automated control systems. The paper describes a systematic methodology for evaluating whether the interface provides the necessary information about the machine to enable the operator to perform a specified task successfully and unambiguously. It also addresses the adequacy of information provided to the user via training material (e.g., user manual) about the machine's behavior. The essentials of the methodology, which can be automated and applied to the verification of large systems, are illustrated by several examples and through a case study of pilot interaction with an autopilot aboard a modern commercial aircraft. The expected application of this methodology is an augmentation and enhancement, by formal verification, of human-automation interfaces.

A computer aided process planning system for concurrent engineering

This paper present ProPlanner, a hybrid computer aided process planning (CAPP) system designed to facilitate concurrent product development. ProPlanner automates information acquisition, product design interpretation, manufacturing operation planning, cutting tool selection, set-up planning and operation sequencing. The system employs a hybrid approach utilizing a combination of rule-based reasoning and object-oriented programming. It enables the early detection of design errors during the design stage before manufacturing and incorporates a feedback mechanism for correcting errors and giving suggestions to modify the product design.

Integrating virtual 3-D display systems into product design reviews: some insights from empirical testing

The infusion of virtual three-dimensional (3-D) display systems into the product design and development process has intrigued researchers and practitioners in recent years. However, the variety of commercially available devices has complicated system selection and use for this application. This paper presents results of a study designed to determine if virtual display systems contribute to cross-functional team collaboration during product design reviews. The research conducted at a US Army design facility investigates design team use of virtual environments (VEs) for evaluation of a new armoured vehicle-refuelling concept. Study results indicated that teams detect more design errors when using stereoscopic glasses or conventional monoscopic cathode ray tube (CRT) monitor systems, they detect design errors faster using a head mounted display (HMD), and no differences were found for the time to resolve identified design problems. Subjective perceptions and preferences data analyses indicated that HMD and CRT monitor systems were liked best.

On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays

Design validation for embedded arrays remains as a challenging problem in today's microprocessor design environment. At Somerset, validation of array designs relies on both formal verification and vector simulation. Although several methods for array design validation have been proposed and had great success [Ganguly et al. 1996; Pandey et al. 1996, 1997; Wang and Abadir 1997], little evidence has been reported for the effectiveness of these methods with respect to the detection of design errors. In this paper, we measure the effectiveness of different validation approaches based on automatic design error injection and simulation. The technique provides a systematic way to evaluate various validation approaches at both logic and transistor levels. Experimental results on recent PowerPC microprocessor arrays will be discussed and reported.

The model checker SPIN

SPIN is an efficient verification system for models of distributed software systems. It has been used to detect design errors in applications ranging from high-level descriptions of distributed algorithms to detailed code for controlling telephone exchanges. The paper gives an overview of the design and structure of the verifier, reviews its theoretical foundation, and gives an overview of significant practical applications.