Detailed SPICE Simulations Research Articles

P‐1.6: Design of High Charge Gain Oxide TFTs Based Active Pixel Sensing Circuit

Dynamic X‐ray detecting for large area medical imaging requires high‐gain and stable Active Pixel Sensor (APS) circuit integrated with Thin Film Transistors (TFTs). In this paper, the APS circuit using oxide TFTs is studied based on the small‐signal model, and the charge gain and effects of threshold voltage shift (ΔVth) are investigated. Detailed SPICE simulations show the charge gain of the APS circuit of the oxide TFTs is 234 × of that of the conventional a‐Si:H TFT PPS circuit.

An Approximate Memory Based Defense Against Model Inversion Attacks to Neural Networks

Diverse and comprehensive training data is critical in building robust machine learning (ML) models. However, model inversion attacks (MIA) have demonstrated that an ML model can leak important information about its training dataset. This work examines the existing MIAs and proposes a hardware-oriented solution to protect the training data from such attacks. Our proposed solution – MIDAS: Model Inversion Defenses with an Approximate memory System – intentionally introduces memory faults to thwart MIA without compromising the original ML model. We use detailed SPICE simulations to build the DRAM fault model with voltage overscaling, implement the state-of-the-art MIAs, and evaluate our proposed solution. Our experiments demonstrate that MIDAS can effectively protect training data from run-time adversarial attacks. In terms of the Pearson Correlation Coefficient (PCC) similarity measure (between the original and the recovered training data), MIDAS reduces the PCC value for shallow and deep neural networks.

Comparative evaluation of SiC/GaN “MOSFET” transistors under different switching conditions

The aim of this paper is to conduct a mutual comparison of switching energy losses in cascade gallium nitride (GaN) and silicon "super junction" MOSFET” transistor, in both cases designed for a maximum operating voltage of (650 V). For the analysis of switching characteristics of transistors used double pulse test method by using detailed SPICE simulation model. Data on transient on and off processes were generated using the “LTspice” simulation package in a wide range of drain currents with two different gate resistance values of the tested transistors. The total energy losses in the GaN have been simulated during one transistor at (on and off cycle). The obtained results indicate that the superior switching characteristics of GaN devices for a drain current of (30 A) is five to eight times less than the switching characteristics of silicon “MOSFET” transistor when compared to silicon components, especially during operation of transistors with high drain currents.

AUTO-APPRAISAL OF VOLTAGE RATING FOR SWITCHED-CAPACITOR DC-DC CONVERTERS

Resonant Switched Capacitor (SC) DC-DC converters are showing potential for use in medium to high-power applications. The high-cell count in these applications means that for a given voltage conversion ratio there are theoretically a large number of alternative topologies that can be synthesised. However, each of these topologies may exhibit different competing characteristics, for example total VA rating of capacitors, total VA rating of switches, number of switches and individual switch voltage rating. Obtaining an optimum topology in terms of given design constraints is therefore important requirement. This paper builds on previous work by the authors by presenting a method for the automatic calculation of the voltage ratings of the components in a SC converter. This result along with earlier work, allows for the calculation of VA ratings, which are an important metric when comparing competing circuits. In addition, a new Canonical Cell topology is presented that extends the range of SC circuits that can be analysed using this method, to cover so-called Ladder circuits. The method is validated against detailed Spice simulations and measurements from a hardware prototype.

An Algorithm for Automatically Calculating Component Current Ratings in Switched-Capacitor DC-DC Converters

Switched capacitor (SC) dc–dc converters, which have traditionally been used for on-chip power supplies, are now being considered for medium to high-power applications. This paper presents a method for automatically synthesizing SC converters as well as deriving the expressions for their charge-multipliers. Charge multipliers can be used to calculate important design characteristics such as converter output voltage regulation, efficiency, and component current ratings, which can then be used to appraise different topologies. However, whilst a full appraisal of converters also requires component voltage ratings, this work is the first step in developing an automatic software tool that will employ a search-based algorithm to generate optimum SC topologies for a given application. The method is based on the proposition that all SC converters can be synthesized from a so-called “basic cell”. The automatic derivation and solution of the charge transfer equations for a traditional Fibonacci SC converter is presented as an example of the proposed method, which is validated against existing analytic equations as well as a detailed Spice simulation. The automatic calculation of the charge-multipliers for two other well-known SC converters is also demonstrated, including a new, arbitrarily generated circuit, which again is validated against detailed spice simulations.

A fast training method for memristor crossbar based multi-layer neural networks

Memristor crossbar arrays carry out multiply–add operations in parallel in the analog domain which is the dominant operation in a neural network application. On-chip training of memristor neural network systems have the significant advantage of being able to get around device variability and faults. This paper presents a novel technique for on-chip training of multi-layer neural networks implemented using a single crossbar per layer and two memristors per synapse. Using two memristors per synapse provides double the synaptic weight precision when compared to a design that uses only one memristor per synapse. Proposed system utilizes a novel variant of the back-propagation (BP) algorithm to reduce both circuit area and training time. During training, all the memristors in a crossbar are updated in four steps in parallel. We evaluated the training of the proposed system with some nonlinearly separable datasets through detailed SPICE simulations which take crossbar wire resistance and sneak-paths into consideration. The proposed training algorithm trained the nonlinearly separable functions with a slight loss in accuracy compared to training with the traditional BP algorithm.

On-chip training of memristor crossbar based multi-layer neural networks

Memristor crossbar arrays carry out multiply-add operations in parallel in the analog domain, and so can enable neuromorphic systems with high throughput at low energy and area consumption. On-chip training of these systems have the significant advantage of being able to get around device variability and faults. This paper presents on-chip training circuits for multi-layer neural networks implemented using a single crossbar per layer and two memristors per synapse. Using two memristors per synapse provides double the synaptic weight precision when compared to a design that uses only one memristor per synapse. Proposed on-chip training system utilizes the back propagation (BP) algorithm for synaptic weight update. Due to the use of two memristors per synapse, we utilize a novel technique for error back propagation. We evaluated the training of the system with some nonlinearly separable datasets through detailed SPICE simulations which take crossbar wire resistance and sneak-paths into consideration. Our results show that in the proposed design, the crossbars consume about 9× less power than single memristor per synapse design.

Improving the energy efficiency of reversible logic circuits by the combined use of adiabatic styles

One of the most prominent issues in fully adiabatic circuits is the breaking reversibility problem; i.e., non-adiabatic energy dissipation in the last stage adiabatic gates whose outputs are connected to external circuits. In this paper, we show that the breaking reversibility problem can result in significant energy dissipation. Subsequently, we propose an efficient technique to address the breaking reversibility problem, which is applicable to the usual fully adiabatic logic such as 2LAL, SCRL, and RERL. Detailed SPICE simulations are used to evaluate the proposed technique. The experimental results show that the proposed technique can considerably reduce (e.g., about 74% for RERL, 35% for 2LAL, and 17% for SCRL) the energy dissipation arising from the breaking reversibility problem.

Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies[Note 1

Single event upsets (SEUs) and single event transients (SETs) are major reliability concerns in deep submicron technologies. As technology feature size shrinks, digital circuits are becoming more susceptible to SEUs and SETs. A novel SEU/SET-tolerant latch called feedback redundant SEU/SET-tolerant latch (FERST) is presented, where redundant feedback lines are used to mask SEUs and delay elements are used to filter SETs. Detailed SPICE simulations have been done to evaluate the proposed design and compare it with previous latch designs. The results show that the SEU tolerance of the FERST latch is almost equal to that of a TMR latch (a widely used latch which is the most reliable among the previous latches); however, the FERST latch consumes about 50% less energy and occupies 42% less area than the triple modular redundancy (TMR) latch. Furthermore, the results show that more than 90% of the injected SETs can be masked by the FERST latch if the delay size is properly selected.

A novel radiation hardened by design latch

Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-event-upset (SEU) immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes.

Hierarchical constraint transformation based on genetic optimization for analog system synthesis

In a top–down analog system design methodology, the task of translating high-level performance specifications and constraints into component level parameters is termed as constraint transformation. In this paper, we presented a genetic optimization based approach to constraint transformation. The salient features of this are a search space profiling technique and a hierarchical two-level genetic optimization engine. Performance estimation for profiling and hierarchical optimization uses both the performance equations embedded in an analog performance estimation module as well as detailed SPICE simulation. We described the constraint transformation method, and each of its constituents. The effectiveness of the two-level hierarchical approach was established by comparing it against a flat non-hierarchical method. Application of the constraint transformation method in the synthesis of design examples was also presented in the paper.

IDAP: A Tool for High-Level Power Estimation of Custom Array Structures

While array structures are a significant source of power dissipation, there is a lack of accurate high-level power estimators that account for varying array circuit implementation styles. We present a methodology and a tool, the implementation-dependent array power (IDAP) estimator, that model power dissipation in SRAM-based arrays accurately based on a high-level description of the array. The models are parameterized by the array operations and various technology dependent parameters. The methodology is generic and the IDAP tool has been validated on industrial designs across a wide variety of array implementations in the e500 processor core (e500 is the Motorola processor core that is compliant with the PowerPC Book E architecture). For these industrial designs, IDAP generates high-level estimates for dynamic power dissipation that are accurate with an error margin of less than 22.2% of detailed (layout extracted) SPICE simulations. We apply the tool in three different scenarios: 1) identifying the subblocks that contribute to power significantly; 2) evaluating the effect of bitline-voltage swing on array power; and 3) evaluating the effect of memory bit-cell dimensions on array power.

Circuit and application aspects of tunnelling devices in a MOBILE configuration

AbstractIn this paper, circuit and application aspects of different monostable–bistable transition logic elements (MOBILEs) are analysed. By taking advantage of the multi‐state behaviour of resonant tunnelling devices (RTD) the logic depth and the circuit complexity per logic function is reduced at the gate level. Both, simulation and measurement results prove correct circuit operation in the gigahertz regime and I–O compatibiliy of the logic voltage levels. The scaling laws of the different MOBILEs are compared to each other in terms of speed and power dissipation. Detailed SPICE simulations based on experimental data precisely analyse the impact of fluctuations on the circuit functionality and performance. This study demonstrates that RTD‐based MOBILEs are ready for use in digital circuitry such as linear threshold gates which offer a highly reduced circuit complexity. Copyright © 2003 John Wiley & Sons, Ltd.

CMOS op-amp sizing using a geometric programming formulation

The problem of CMOS op-amp circuit sizing is addressed here. Given a circuit and its performance specifications, the goal is to automatically determine the device sizes in order to meet the given performance specifications while minimizing a cost function, such as a weighted sum of the active area and power dissipation. The approach is based on the observation that the first order behavior of a MOS transistor in the saturation region is such that the cost and the constraint functions for this optimization problem can be modeled as posynomial in the design variables. The problem is then solved efficiently as a convex optimization problem. Second order effects are then handled by formulating the problem as one of solving a sequence of convex programs. Numerical experiments show that the solutions to the sequence of convex programs converge to the same design point for widely varying initial guesses. This strongly suggests that the approach is capable of determining the globally optimal solution to the problem. Accuracy of performance prediction in the sizing program (implemented in MATLAB) is maintained by using a newly proposed MOS transistor model and verified against detailed SPICE simulation.

Manufacturability and robust design of nanoelectronic logic circuits based on resonant tunnelling diodes

The manufacturability of logic circuits based on quantum tunnelling devices, namely double-barrier resonant tunnelling diodes (RTD), is studied in detail. The homogeneity and reproducibility of III/V mesa technology-based devices is experimentally evaluated and interpreted using multiple I-V characteristic simulations. The experimental sensitivity of the RTD I-V parameters on well and barrier thickness is compared with multiple I-V simulations. With shrinking minimum feature size the fluctuations in the peak current can be directly attributed to an RTD area variation caused by the increasing impact of lithography and etching on lateral dimensions. These results prove that the III/V technology fulfils the requirements for a large scale integration of RTD devices. A nanoelectronic circuit architecture based on an improved MOBILE threshold logic gate is presented. Detailed SPICE simulations using the experimental data show that clock and supply voltage fluctuations are tolerated up to ± 0.1 V at a supply voltage of 0.7 V. Very strong local peak voltage variations of 15 per cent in opposite directions would be necessary to have a critical impact on to the circuit functionality. Smaller deviations only affect the timing without degrading the reliability of the circuit. Consequently, the design of a stable power supply and clocking scheme is more important for the overall circuit performance than the small relative deviations of the RTD peak voltage.

Soft-switching single-stage AC-to-DC converter with low harmonic distortion

A 1 /spl phi/ high-frequency (HF) transformer isolated, soft-switching single-stage ac-dc converter with low line-current harmonic distortion is presented. Its operation is explained with equivalent circuits for the various intervals. The converter is analyzed and design curves are obtained. An optimization parameter is introduced and a systematic design procedure is illustrated with a design example. Detailed SPICE simulation and experimental results of a 500 W converter with load as well as line voltage variation are given to verify theory. The proposed converter employs a zero-voltage transition (ZVT) network to ensure zero-voltage switching (ZVS) at all loads, and natural power factor correction is ensured using a simple control circuit.

Analysis and design of a fixed-frequency LCL-type series-resonant converter with capacitive output filter

A fixed-frequency modified (LCL-type) series-resonant converter which uses a capacitive output filter is analysed using the Fourier series approach. Based on the analysis a simple design procedure is given. Detailed SPICE simulation results are presented for the designed converter to evaluate its performance for varying input supply voltage and for load variation. Experimental results obtained from a MOSFET based 500 W, 115 V output converter are presented to verify the analysis. The converter operates in lagging power factor mode for a very wide variation in the load and the supply voltage and is suitable for high voltage output applications.

Laddering wave in serpentine delay line

The backward propagating crosstalk among the sections of a serpentine delay line accumulates to appear as a laddering wave in the receiving waveform. This occurrence results in severe signal distortion and may significantly reduce the desired time delay. A novel wave tracing analysis is proposed to describe qualitatively the waveform of the laddering wave. Furthermore, a quantitative analysis based on the modal decomposition theory is derived to predict the level of each ladder. The theory has been verified from the comparison of the numerical results with those obtained by the detailed SPICE simulation and the TDT measurement. >

Novel analogue VLSI design for multilayer networks

The paper introduces a new pulsestream analogue VLSI design which has been optimised for the implementation of multilayer networks. The requirements of fully-trained multilayer perceptrons have been analysed to produce a set of specifications for the hardware design. The pulse-stream circuits described in the paper are driven from a fixed-frequency master clock, and a synaptic multiply-and-add computation is performed with every pulse. Detailed SPICE simulations have been carried out, and preliminary results from a set of test chips are also presented.

Design and performance of "1.25-µm" CMOS for digital applications

This paper presents a detailed approach for the design and performance analysis of 1.25-µm CMOS digital circuit technology based on relatively simple sets of fundamental device parametric and circuit equations. As a start, a topological and "in-depth" baseline is assumed for this 1.25-µm CMOS technology, based, in part, on a set of achievable lithographic feature sizes and alignment tolerances together with a set of reasonable process geometric parameters. The process baseline is TWIN-WELL CMOS using n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> epi on an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> substrate as the host starting material. Two of the key geometric parameters defined are effective channel length, L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</inf> = 1 µm, and gate oxide thickness, t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</inf> = 250 Å. Other dimensions have been selected using quasi-scaling rules consistent with a 2λ of 1.25 µm. The design process starts with the selection of the average "well" doping levels from a consideration of some key short-channel effects: simple charge sharing and drain-induced barrier lowering (DIBL). The selection of a suitable operating voltage, V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> , is considered during this process as it effects junction breakdown voltage, gate oxide fields, and more importantly, potential hot-electron injection. Additional process design analyses are presented with respect to the establishment of gate threshold voltages and field inversion voltages. A simple transient analysis procedure is developed for a basic inverter structure which yields results close to those obtained through more detailed SPICE simulations. A unit delay (single fan-out) analysis is performed yielding delays of 214 ps for a V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> of 5 V and 270 ps for a V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> of 3.3 V.