Desktop CPU Research Articles

OptiSAIL: A system for the simultaneous retrieval of soil, leaf, and canopy parameters and its application to Sentinel-3 Synergy (OLCI+SLSTR) top-of-canopy reflectances

This paper describes the selected algorithm for the ESA climate change initiative vegetation parameters project. Multi- and hyper-spectral, multi-angular, or multi-sensor top-of-canopy reflectance data call for an efficient generic retrieval system which can improve the consistent retrieval of standard canopy parameters as albedo, Leaf Area Index (LAI), Fraction of Absorbed Photosynthetically Active Radiation (fAPAR) and their uncertainties, and exploit the information to retrieve additional parameters (e.g. leaf pigments). We present a retrieval system for canopy and sub-canopy parameters (OptiSAIL), which is based on a model comprising SAIL (canopy reflectance), PROSPECT-D (leaf properties), TARTES (snow properties), a soil model (soil reflectance anisotropy, moisture effect), and a cloud contamination model. The inversion is gradient based and uses codes created by Automatic Differentiation. The full per pixel covariance-matrix of the retrieved parameters is computed. For this demonstration, single observation data from the Sentinel-3 SY_2_SYN (synergy) product is used. The results are compared with the MODIS 4-day LAI/fAPAR product and PhenoCam site photography. OptiSAIL produces generally consistent and credible results, at least matching the quality of the technically quite different MODIS product. The system is computationally efficient with a rate of 150 pixel s−1 (7 ms per pixel) for a single thread on a current desktop CPU using observations on 26 bands. Not all of the model parameters are well determined in all situations. Significant correlations between the parameters are found, which can change sign and magnitude over time. OptiSAIL appears to meet the design goals and puts real-time processing with this kind of system into reach.

Enabling Space-Based Computed Cloud Tomography with a Mixed Integer Linear Programming Scheduler

Cumuliform clouds in Earth’s lower atmosphere play important roles in the radiative balance and hydrological cycle of the climate system. Yet key processes unfolding in these clouds, such as aerosol interactions and precipitation initiation, are still poorly understood. Current space-based cloud observation methods are inadequate for inferring the internal structure of clouds outside of a narrow transect that is probed actively by radar and lidar. Cloud tomography is an emerging technique that uses passive imaging of a cloud target from multiple locations with a large angular range to infer internal cloud structure. Many low convective clouds only have a lifetime of 15–25 min, necessitating autonomous scheduling of observation targets as they appear. Onboard autonomous scheduling is formulated as a mixed-integer optimization problem (MILP) with a finite time horizon and a reward scheme designed to maximize the angular range of the observations. A finite time horizon MILP scheduler is well suited to this mission because the short lifetime of low convective clouds creates a natural time horizon. This MILP can solve for an optimal observation schedule in a maximum time of 15 ms on a desktop CPU. The MILP scheduler is able to observe nearly 60% more targets than a conventional push-broom camera configuration. This initial result is promising and demonstrates the need for continued research in this area.

A generic deep learning architecture optimization method for edge device based on start-up latency reduction

In the promising Artificial Intelligence of Things technology, deep learning algorithms are implemented on edge devices to process data locally. However, high-performance deep learning algorithms are accompanied by increased computation and parameter storage costs, leading to difficulties in implementing huge deep learning algorithms on memory and power constrained edge devices, such as smartphones and drones. Thus various compression methods are proposed, such as channel pruning. According to the analysis of low-level operations on edge devices, existing channel pruning methods have limited effect on latency optimization. Due to data processing operations, the pruned residual blocks still result in significant latency, which hinders real-time processing of CNNs on edge devices. Hence, we propose a generic deep learning architecture optimization method to achieve further acceleration on edge devices. The network is optimized in two stages, Global Constraint and Start-up Latency Reduction, and pruning of both channels and residual blocks is achieved. Optimized networks are evaluated on desktop CPU, FPGA, ARM CPU, and PULP platforms. The experimental results show that the latency is reduced by up to 70.40%, which is 13.63% higher than only applying channel pruning and achieving real-time processing in the edge device.

Optimising digital signal processor‐based defect detection in smart manufacturing with lightweight convolutional neural networks

AbstractIndustrial defect detection is an important part of intelligent manufacturing, and Internet of things (IoT)‐based defect detection is receiving more and more attention. Although deep learning (DL) can help defect detection reduce the cost and improve the accuracy of traditional manual quality inspection, DL requires huge computational resources and is difficult to be simply deployed on IoT devices with limited computational power and memory resources. Digital signal processor (DSP) is an important IoT device with small size, high performance and low energy consumption, which has been widely used in intelligent manufacturing. In order to perform accurate defect detection on DSP, the authors proposed various optimisation strategies and then used a parallel scheme to scale the model to execute on multiple cores. The authors’ method evaluated it on Northeastern University Surface Defect Dataset, Magnetic Tile Defect Dataset, Rail Surface Defect Dataset and Silk Cylinder Defect Dataset, and the experimental results showed that the authors’ method obtains faster speeds without accuracy loss compared to running the same Convolutional Neural Networks model on a mainstream desktop CPU. This means that the authors’ method can realise efficient and accurate defect detection on IoT devices with limited computational power and memory resources, which opens up new possibilities for future development in the field of smart manufacturing.

DSP-Based Traffic Target Detection for Intelligent Transportation

Internet of Things (IoT)-based intelligent transportation is attracting more and more attention. As a key component of intelligent transportation, traffic video monitoring is very important, in which vehicle and pedestrian detection on the road is a crucial task. Although vehicle and pedestrian detection through deep learning (DL) may achieve high accuracy, it tends to require high computing resources, which hinders its use on IoT devices. As an important class of IoT devices, digital signal processor (DSP) has the characteristics of low energy consumption, small size, and strong performance, which has been widely used in intelligent transportation. In order to use DL on DSP for accurate vehicle and pedestrian detection, we first propose a series of general tactics to optimize the object detection convolutional neural network (CNN) model, including convolution layer optimization, cache optimization, compiler optimization, intrinsics optimization and direct memory access (DMA) acceleration, and then a parallel scheme to extend the model to run on multicore, and further quantize the implementation of the model. We evaluate it on UA-DETRAC and KITTI datasets. Experimental results show that our method achieves a faster speed than running the same CNN model on a mainstream desktop CPU, with only 0.06% accuracy loss.

Optimal real-time resonant scanner linearization using filtered Hermite interpolation.

High-speed laser scanning microscopy frequently relies on resonant scanners due to their order of magnitude increase in imaging rate compared to conventional galvanometer scanners. However, the use of a nonlinear scan trajectory introduces distortion that must be corrected. This manuscript derives a new algorithm based on filtered Hermite polynomial interpolation that provides the optimal shot-noise-limited SNR for a fixed number of photons and provides higher spatial accuracy than previous methods. An open-source library is presented using the Intel advanced vector instruction set (AVX) to process up to 32 samples in parallel. Using this approach, I simultaneously demonstrate lower shot noise variance, moderately higher spatial accuracy and greater than 1 gigapixel per second interpolation rate on a desktop CPU.

RepDI: A light-weight CPU network for apple leaf disease identification

Apple disease is one of the major factors affecting apple production, and the visual diagnosis of apple leaves is an efficient disease identification solution. In this paper, we propose an efficient lightweight model based on structural reparameterization for apple leaf disease identification, called RepDI for short. To achieve faster inference on the CPU devices, we introduce depth-wise separable convolution and structural reparameterization technology in RepDI, which has different structures during training and inference. In addition, to better capture diseased leaves and disease regions in complex contexts, we propose the parallel dilated attention mechanism module and embed it into RepDI. Experiments show that RepDI can achieve state-of-the-art performance in disease identification task, compared to most lightweight models. Meanwhile, RepDI achieves the fastest inference speed on our desktop CPU, which is an important factor in practical applications. Furthermore, we collect and annotate a novel dataset for apple leaf diseases from real scenarios, called Real-ALD, which is more challenging than previous datasets. And RepDI achieves a top-1 accuracy of 98.92 in the Real-ALD dataset under a limited training configuration. Our code is released to contribute to the plant protection community and we will further explore the potential of RepDI for down-stream detection, segmentation tasks.

FPGA-based Acceleration of Time Series Similarity Prediction: From Cloud to Edge

With the proliferation of low-cost sensors and the Internet of Things, the rate of producing data far exceeds the compute and storage capabilities of today’s infrastructure. Much of this data takes the form of time series, and in response, there has been increasing interest in the creation of time series archives in the past decade, along with the development and deployment of novel analysis methods to process the data. The general strategy has been to apply a plurality of similarity search mechanisms to various subsets and subsequences of time series data to identify repeated patterns and anomalies; however, the computational demands of these approaches renders them incompatible with today’s power-constrained embedded CPUs. To address this challenge, we present FA-LAMP, an FPGA-accelerated implementation of the Learned Approximate Matrix Profile (LAMP) algorithm, which predicts the correlation between streaming data sampled in real-time and a representative time series dataset used for training. FA-LAMP lends itself as a real-time solution for time series analysis problems such as classification. We present the implementation of FA-LAMP on both edge- and cloud-based prototypes. On the edge devices, FA-LAMP integrates accelerated computation as close as possible to IoT sensors, thereby eliminating the need to transmit and store data in the cloud for posterior analysis. On the cloud-based accelerators, FA-LAMP can execute multiple LAMP models on the same board, allowing simultaneous processing of incoming data from multiple data sources across a network. LAMP employs a Convolutional Neural Network (CNN) for prediction. This work investigates the challenges and limitations of deploying CNNs on FPGAs using the Xilinx Deep Learning Processor Unit (DPU) and the Vitis AI development environment. We expose several technical limitations of the DPU, while providing a mechanism to overcome them by attaching custom IP block accelerators to the architecture. We evaluate FA-LAMP using a low-cost Xilinx Ultra96-V2 FPGA as well as a cloud-based Xilinx Alveo U280 accelerator card and measure their performance against a prototypical LAMP deployment running on a Raspberry Pi 3, an Edge TPU, a GPU, a desktop CPU, and a server-class CPU. In the edge scenario, the Ultra96-V2 FPGA improved performance and energy consumption compared to the Raspberry Pi; in the cloud scenario, the server CPU and GPU outperformed the Alveo U280 accelerator card, while the desktop CPU achieved comparable performance; however, the Alveo card offered an order of magnitude lower energy consumption compared to the other four platforms. Our implementation is publicly available at https://github.com/aminiok1/lamp-alveo.

Shape-stabilized low melting-point alloy/expanded graphite composite thermal pad with excellent chip heat dissipation performance

• A low melting point alloy/expanded graphite composite thermal pad is prepared. • The oxidation of the alloy is beneficial to its adsorption by expanded graphite. • The composite thermal pad possesses a high thermal conductivity of 26.94 W/m·K. • A very low thermal impedance of 0.42 K·cm 2 /W is achieved by the thermal pad. • The thermal pad shows higher heat dissipation efficiency than the commercial one. Thermal interface materials that possess high thermal conductivity and can reach low thermal impedance during service, are highly desirable for chip heat dissipation systems, especially when cooling high-power chips. Herein, a novel thermal pad was developed by combining low melting point alloy having metal-level thermal conductivity and liquid-like rheological property with expanded graphite possessing large pore volume and high thermal conductivity. Specifically, the alloy 62.5Ga21.5In16Sn was modified by the trace-oxidation method to obtain oxidized alloy, followed by adsorbing into expanded graphite and then molding and pressing to fabricate the thermal pad. It is found that the oxidation treatment resulted in the generation of refractory metal oxides Ga 2 O 3 and SnO 2 within the alloy, thereby preventing the leakage of the alloy from the composite thermal pad. Impressively, the optimal low melting point alloy/expanded graphite composite thermal pad, prepared at the oxidation duration of 24 min, expanded graphite mass fraction of 4 % and compact density of 3.125 g/cm 3 , reached a thermal conductivity of as high as 26.94 W/m·K and a thermal impedance of as low as 0.42 K·cm 2 /W, along with exhibiting a good shape-stability. More significantly, when employed into a simulative desktop CPU cooling system, this thermal pad exhibited 36.78 % higher cooling efficiency under the forced air convection, extended ten times in the time for the chip to reach the upper limit temperature (100 ℃) under the natural air cooling, and benefited to the chip to fight with the pulse-type instantaneous thermal shock, as compared to the commercial thermal pad. These excellent characteristics and good heat dissipation performance make the low melting point alloy/expanded graphite composite thermal pad show great potential for use in chip thermal management systems.

Computing efficiency of XBeach hydro- and wave dynamics on Graphics Processing Units (GPUs)

Numerical prediction of coastal inundation can be complex due to the multiple physical processes involved and typically requires two-dimensional numerical model extents, particularly in areas with complex along-shore morphology. Such model domains often incur relatively high computational expense. Recent extreme inundation studies for Wellington, New Zealand, were executed using the numerical tool, XBeach. Here, the two-dimensional physical dynamics associated with multiple small embayments and both reef and sandy beach substrates, require large, high spatial resolution numerical model extents, informed by a multi-source elevation surface. XBGPU, is a translation of key XBeach features into code that permits GPU-based acceleration. The present study presents a comparison between XBeach and XBGPU for the same numerical model configuration and extents. Three model resolutions were employed, ranging from a typical desktop CPU based XBeach model resolution, to the highest resolution model that will require High Performance Computing (HPC) scale resources. Two CPU HPC facilities were used and five GPUs to investigate the scalability of both XBeach and XBGPU. The latter ranged from desktop grade units to GPUs associated with professional computing facilities. XBeach scalability is investigated by mean of the speed-up ratio, the time saving ratio and the computational efficiency. These are in reference to the computational speed of a model running on one CPU core. The XBGPU speed-up ratio is presented as a function of the slowest GPU. Direct comparisons between XBeach and XBGPU were achieved by using computational capacity as a metric. The results indicate that even a desktop grade GPU can compete with the computational efficiency of HPC-scale CPU facilities. Small model resolutions presented inefficient scaling on both high-performance CPUs and GPUs while the high-resolution model presented near linear scalability for the high-performance GPUs. Nevertheless, HPCs can be efficient to solve large computational problems if enough CPUs are employed.

An efficient hybrid hash based privacy amplification algorithm for quantum key distribution

Privacy amplification (PA) is an essential part in a quantum key distribution (QKD) system, distilling a highly secure key from a partially secure string by public negotiation between two parties. The optimization objectives of privacy amplification for QKD are large block size, high throughput and low cost. For the global optimization of these objectives, a novel privacy amplification algorithm is proposed in this paper by combining multilinear-modular-hashing and modular arithmetic hashing. This paper proves the security of this hybrid hashing PA algorithm within the framework of both information theory and composition security theory. A scheme based on this algorithm is implemented and evaluated on a CPU platform. The results on a typical CV-QKD system indicate that the throughput of this scheme ( $$261\,\mathrm{Mbps}@2.6\times 10^8$$ input block size) is twice higher than the best existing scheme ( $$140\,\mathrm{Mbps}@1\times 10^8$$ input block size). Moreover, this scheme is implemented on a mobile CPU platform instead of a desktop CPU or a server CPU, which means that this algorithm has a better performance with a much lower cost and power consumption.

Cardiac Magnetic Resonance Left Ventricle Segmentation and Function Evaluation Using a Trained Deep-Learning Model

Cardiac MRI is the gold standard for evaluating left ventricular myocardial mass (LVMM), end-systolic volume (LVESV), end-diastolic volume (LVEDV), stroke volume (LVSV), and ejection fraction (LVEF). Deep convolutional neural networks (CNNs) can provide automatic segmentation of LV myocardium (LVF) and blood cavity (LVC) and quantification of LV function; however, the performance is typically degraded when applied to new datasets. A 2D U-net with Monte-Carlo dropout was trained on 45 cine MR images and the model was used to segment 10 subjects from the ACDC dataset. The initial segmentations were post-processed using a continuous kernel-cut method. The refined segmentations were employed to update the trained model. This procedure was iterated several times and the final updated U-net model was used to segment the remaining 90 ACDC subjects. Algorithm and manual segmentations were compared using Dice coefficient (DSC) and average surface distance in a symmetric manner (ASSD). The relationships between algorithm and manual LV indices were evaluated using Pearson correlation coefficient (r), Bland-Altman analyses, and paired t-tests. Direct application of the pre-trained model yielded DSC of 0.74 ± 0.12 for LVM and 0.87 ± 0.12 for LVC. After fine-tuning, DSC was 0.81 ± 0.09 for LVM and 0.90 ± 0.09 for LVC. Algorithm LV function measurements were strongly correlated with manual analyses (r = 0.86–0.99, p < 0.0001) with minimal biases of −8.8 g for LVMM, −0.9 mL for LVEDV, −0.2 mL for LVESV, −0.7 mL for LVSV, and −0.6% for LVEF. The procedure required ∼12 min for fine-tuning and approximately 1 s to contour a new image on a Linux (Ubuntu 14.02) desktop (Inter(R) CPU i7-7770, 4.2 GHz, 16 GB RAM) with a GPU (GeForce, GTX TITAN X, 12 GB Memory). This approach provides a way to incorporate a trained CNN to segment and quantify previously unseen cardiac MR datasets without needing manual annotation of the unseen datasets.

異種混合プロセッサにおける並列FEMコードの性能評価

The main computations in finite element analysis are basic linear algebra operations on matrices and vectors, and even load distribution is suitable for these parallel computations. Therefore, parallel FEM codes implemented with OpenMP and simple scheduling often achieve good efficiency in conventional multi-core processors. However, in recent years, desktop CPUs such as Intel's Alder Lake and Apple's M1 have adopted heterogeneous architectures with high-efficiency and high-performance cores. Therefore, it is unclear whether the conventional parallel FEM code can extract the processor's performance on those parallel computers. This research evaluates the performance of a heterogeneous processor using a parallel FEM code that uses the conjugate gradient method as a linear solver and discusses the results.

PT-NAS: Designing efficient keypoint-based object detectors for desktop CPU platforms

Recently, keypoint-based object detectors have attracted widespread attention, due to their novel structure and excellent performance. However, in terms of their design, there are still two limitations: 1) Most keypoint-based methods are designed for GPU platforms, which makes them inefficient on desktop CPU platforms. 2) Existing works still rely heavily on manual design and prior knowledge. To this end, this work aims to offer a practical solution for designing CPU-efficient key-point detectors. First, we present a set of practical design guidelines by comparing different detection architectures. Following the proposed guidelines, we further develop a progressive three-phase network architecture search (PT-NAS) to achieve the automated design of detection architectures. Benefiting from our hierarchical search space and novel search pipeline, our PT-NAS not only achieves higher search efficiency, but also satisfies the practicality of CPU platforms. On the MS-COCO benchmark, we utilize our PT-NAS to generate several key-point detectors for fast inference on desktop CPUs. Finally, comprehensive comparison experiments prove that the proposed PT-NAS can produce new state-of-the-art keypoint-based detectors for CPU platforms.

Signal processing for a reverse‐GPS wildlife tracking system: CPU and GPU implementation experiences

AbstractWe present robust high‐performance implementations of signal‐processing tasks performed by a high‐throughput wildlife tracking system called ATLAS. The system tracks radio transmitters attached to wild animals by estimating the time of arrival of radio packets to multiple receivers (base stations). Time‐of‐arrival estimation of wideband radio signals is computationally expensive, especially in acquisition mode (when the time of transmission is not known, not even approximately). These computations are a bottleneck that limits the throughput of the system. We developed a sequential high‐performance CPU implementation of the computations a few years back, and more recently a GPU implementation. Both strive to balance performance with simplicity, maintainability, and development effort, as most real‐world codes do. The article reports on the two implementations and carefully evaluates their performance. The evaluations indicates that the GPU implementation dramatically improves performance and power‐performance relative to the sequential CPU implementation running on a desktop CPU typical of the computers in current base stations. Performance improves by more than 50X on a high‐end GPU and more than 4X with a GPU platform that consumes almost 5 times less power than the CPU platform. Performance‐per‐Watt ratios also improve (by more than 16X), and so do the price‐performance ratios.

Research on Post-Quantum Cryptosystem Based on IoT Devices

With the emergence of quantum computers, public-key cryptographic algorithms commonly used in classical computers are no longer secure. However, the current post-quantum cryptographic algorithms are mainly concentrated on the desktop CPU of Intel and AMD. For the Internet of Things, which is increasingly widely used, the research on post-quantum cryptographic algorithms is still scarce. Based on the research of post-quantum cryptosystem, this paper explores the post-quantum key algorithm based on Internet of Things devices.

DcaNAS: efficient convolutional network Design for Desktop CPU platforms

The hardware platform is a significant consideration in efficient CNN model design. Most lightweight networks are based on GPUs and mobile devices. However, they are usually not efficient nor fast enough for desktop CPU platforms. In this paper, we aim to explore the design of highly-efficient convolutional architectures for desktop CPU platforms. To achieve our goal, we first derive a series of CNN model design guidelines for CPU-based devices by comparing different computing platforms. Based on these proposed guidelines, we further present a Desktop CPU-Aware network architecture search (DcaNAS) to search for the optimal network structure with lower CPU latency. By combining automatic search and manual design, our DcaNAS achieves better flexibility and efficiency. On the ImageNet benchmark, we employ DcaNAS to produce two CPU-based lightweight CNN models: DcaNAS-L for higher accuracy and DcaNAS-S for faster speed. On a single CPU core, DcaNAS-L achieves 78.8% Top-1 (94.6% Top-5) accuracy at 13.6 FPS (73.5 ms), and our DcaNAS-S achieves extremely low CPU latency (43.1 ms). The results show that our DcaNAS method can obtain new state-of-the-art CPU-based networks.

Side-Channel Attacks With Multi-Thread Mixed Leakage

Side-channel attacks are one of the greatest practical threats to security-related applications, because they are capable of breaking ciphers that are assumed to be mathematically secure. Lots of studies have been devoted to power or electro-magnetic (EM) analysis against desktop CPUs, mobile CPUs (including ARM, MSP, AVR, etc) and FPGAs, but rarely targeted modern GPUs. Modern GPUs feature their special and specific single instruction multiple threads (SIMT) execution fashion, which makes their power/EM leakage more sophisticated in practical scenarios. In this article, we study side-channel attacks with leakage from SIMT systems, and propose leakage models suited to any SIMT systems and specifically to CUDA-enabled GPUs. Afterwards, we instantiate the models with a GPU AES implementation, which is also used for performance evaluations. In addition to the models, we provide optimizations on the attacks that are based on the models. To evaluate the models and optimizations, we run the GPU AES implementation on a CUDA-enabled GPU and, at the same time, collect its EM leakage. The experimental results show that the proposed models are more efficient and the optimizations are effective as well. Our study suggests that GPU-based cryptographic implementations may be much vulnerable to microarchitecture-based side-channel attacks. Therefore, GPU-specific countermeasures should be considered for GPU-based cryptographic implementations in practical applications.

RGB-D camera calibration and trajectory estimation for indoor mapping

In this paper, we present a system for estimating the trajectory of a moving RGB-D camera with applications to building maps of large indoor environments. Unlike the current most researches, we propose a ‘feature model’ based RGB-D visual odometry system for a computationally-constrained mobile platform, where the ‘feature model’ is persistent and dynamically updated from new observations using a Kalman filter. In this paper, we firstly propose a mixture of Gaussians model for the depth random noise estimation, which is used to describe the spatial uncertainty of the feature point cloud. Besides, we also introduce a general depth calibration method to remove systematic errors in the depth readings of the RGB-D camera. We provide comprehensive theoretical and experimental analysis to demonstrate that our model based iterative-closest-point (ICP) algorithm can achieve much higher localization accuracy compared to the conventional ICP. The visual odometry runs at frequencies of 30 Hz or higher, on VGA images, in a single thread on a desktop CPU with no GPU acceleration required. Finally, we examine the problem of place recognition from RGB-D images, in order to form a pose-graph SLAM approach to refining the trajectory and closing loops. We evaluate the effectiveness of the system on using publicly available datasets with ground-truth data. The entire system is available for free and open-source online.

Harnessing CPU Electromagnetic Emanations for Resonance-Induced Voltage-Noise Characterization

Worst-case dI/dt voltage noise is typically characterized post-silicon using direct voltage measurements through either on-package measurement points or on-chip dedicated circuitry. These approaches consume expensive pad resources or suffer from design-time and run-time overheads. This work proposes an alternative non-intrusive, zero-overhead approach for post-silicon dI/dt voltage noise characterization based on sensing CPU electromagnetic emanations using an antenna and a spectrum analyzer. This approach is based on the observation that high amplitude electromagnetic emanations are correlated with high resonance-induced voltage-noise. This approach enables essential Power-Delivery Network characterization tasks such as: a) obtaining the first-order resonance-frequency of the Power-Delivery LC-tank network, and b) automatically generating voltage noise (dI/dt) stress tests with a genetic-algorithm that is driven by the electromagnetic signal amplitude. The generality of the approach is established by successfully applying it to four different CPUs: two ARM multi-core mobile CPU clusters hosted on a big.LITTLE configuration, one x86-64 AMD desktop CPU and one ARM 64bit 8-core clustered architecture server CPU. The efficacy of the proposed methodology is validated through V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> and direct voltage-noise measurements. Furthermore, the effectiveness of the EM approach to generate dI/dt viruses that have higher V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> that conventional workloads is demonstrated with a dynamic-voltage-scaling (DVS) governor that scales the voltage according to the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> of the EM generated dI/dt viruses for various core-allocations scenarios. For a 62-hour test with a varying workload mix and core allocations, this governor provides safe below nominal-voltage operation.