Design Technology Co-optimization Research Articles

ResNet Modeling for 12 nm FinFET Devices to Enhance DTCO Efficiency

In this paper, a deep learning-based device modeling framework for design-technology co-optimization (DTCO) is proposed. A ResNet surrogate model is utilized as an alternative to traditional compact models, demonstrating high accuracy in both single-task (I–V or C–V) and multi-task (I–V and C–V) device modeling. Moreover, transfer learning is applied to the ResNet model, using the BSIM-CMG compact model for a 12 nm FinFET SPICE model as the pre-trained source. Through this approach, superior modeling accuracy and faster training speed are achieved compared to a ResNet surrogate model initialized with random weights, thereby meeting the rapid and efficient demands of the DTCO process. The effectiveness of the ResNet surrogate model in circuit simulation for 12 nm FinFET devices is demonstrated.

Multi-objective optimization and inverse design of complementary field-effect transistor using combined approach of machine learning and non-dominated sorting genetic algorithms for next-generation semiconductor devices

Complementary field-effect transistors (CFETs), which are structures in which different types of transistors are vertically stacked with a shared control gate, are being focused on for continuing to satisfy Moore's law by overcoming the limitations in pitch scaling. The structures of semiconductor devices become more complex as technology node shrinks, and interrelated multivariate parameters increase. In addition, predicting problems and proposing solutions by identifying complex patterns within extensive data collected for emerging semiconductor designs pose significant computational challenges and are inherently difficult. As a breakthrough in design technology co-optimization for advanced devices, this study developed a novel optimization framework integrating technology computer-aided design simulations, machine learning, and non-dominated sorting genetic algorithms. The developed framework provides unbiased optimal solutions, even in a high-dimensional objective space, while considering the tradeoff relationships between multiple variables. In addition, it enables inverse design to identify the design parameters of devices that satisfy specific electrical performance criteria using only a forward model, while achieving an error rate of less than 2%. Using this framework, we analyzed the operational mechanism of CFETs by comparing the inverse designs of various devices. This novel approach is particularly important when the design space is complex and extensive and is well suited for developing devices that emerge with technological advancements in the semiconductor industry.

(Invited) Advanced Compute Scaling: A New Era of Exciting, Sustainability-Aware Innovations with Nanosheet-Based Devices, Increased Interdisciplinary Synergies, and (R)Evolution Towards Higher Versatility

The need for increased computing keeps growing at an ultra-fast speed, required to support an ever larger and wider range of applications [1]. Meanwhile, recent advances in 3D and photonic technologies are allowing new connectivity possibilities besides the typical on-chip interconnects at system-on-chip (SoC) level. This is enabling a system (r)evolution towards smart disintegration, moving away from a one-meets-all-requirements general-purpose CMOS platform, and allowing higher flexibility by separately designing and fabricating the blocks that are assembled in the final system [2]. Boosted by the novel scaling options enabled by this new approach, logic standard cell shrinkage remains at the core of the compute roadmap. Its momentum is expected to carry on by introducing new device architectures, materials, and scaling boosters such as backside (BS) power delivery (PD) [3-9]. Guided by design-technology-co-optimization (DTCO)-driven design improvements, in close interaction with the adoption of system-technology-co-optimization (STCO), the roadmap also increasingly requires EUV/high-NA EUV lithography for cost-effective, lower energy consumption, continued dimensional scaling.At transistor level, finFETs are being replaced by nanosheet (NS) FETs consisting of several vertically stacked NS per device [10,11]. Beyond that, 3D stacked CMOS, also called CFET [9,12,13], where different polarity NSFETs are folded on top of each other, appears as the ultimate scaling limit of the NS-based transistor’s family. Moreover, changes in how devices are connected are also being introduced. Moving PD to the wafer’s BS, though being a considerable disruptive technological change, is a game changer for on-chip power distribution, enabling smaller IR-drop values. This concept can be implemented in various ways, and has the potential to expand towards other functions, namely by addition of specific devices after BS processing, paving the way towards a truly functional BS [3,9,14]. Two examples of benefits brought by increased BS use are: 1) considerably more compact ESD diodes, with improved latch-up immunity, and BS contacts [9,15]; 2) lower clock latency values by moving the clock’s signal to the BS [9,16].Furthermore, as transistors are now sandwiched and accessed from levels above and below them, this also enables interesting new opportunities for device engineering. Focusing on the highly scalable BS PD scheme wherein the transistor’s source (S) (for bottom FET in case of CFET) is directly contacted from the BS (BSC-S) (Fig.1) [7,9,17,18], while the other terminals remain connected from the wafer’s frontside, several options to optimize the BSC-S’s contact resistance can be considered. These include ways to enlarge its contact surface area and the possible addition of an extra low-temperature, low-resistivity epitaxial layer [9,19,20] prior to metallization. Fig.2 also highlights the need to account for the impact on thermal performance when selecting (BSC-S)-based device configurations and materials [7,9]. Additionally, the intrinsically asymmetric S/drain (D) access with BSC-S can also be explored to enable a simpler path to build devices with differently doped S/D [9]. This can be especially interesting for high-mobility, low-bandgap FETs to mitigate IOFF concerns while still taking advantage of their high-drivability potential. CFET using, e.g., bonding technology for the bottom/top channels and their vertical isolation’s definition can also be particularly suitable for implementing distinct channel materials (like Ge-rich for bottom PMOS) as they are in separate planes.Overall, compute systems, guided by DTCO/STCO with the embrace of the use of both wafer sides, 3D stacking and sequential technologies, can potentially be assembled in ways enabling much more versatile, hybridized platforms. This can allow not only new paths for continued compute/logic scaling, but also ease the introduction of new/alternative device architectures (and materials) as they do not need to meet all the requirements of a general-purpose platform.

Design Technology Co-Optimization for Gate-All-Around Nanosheet Transistors Considering Source/Drain Confinement and Post- Gate Single Diffusion Break

Design Technology Co-Optimization for Gate-All-Around Nanosheet Transistors Considering Source/Drain Confinement and Post- Gate Single Diffusion Break

System and Design Technology Co-Optimization of SOT-MRAM for High-Performance AI Accelerator Memory System

System and Design Technology Co-Optimization of SOT-MRAM for High-Performance AI Accelerator Memory System

Design Technology Co-Optimization for the DRAM Cell Structure With Contact Resistance Variation

Design Technology Co-Optimization for the DRAM Cell Structure With Contact Resistance Variation

Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node

Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node

Application of Generative Adversarial Networks for Virtual Silicon Data Generation and Design-Technology Co-Optimization: A Study on WAT and CP

Application of Generative Adversarial Networks for Virtual Silicon Data Generation and Design-Technology Co-Optimization: A Study on WAT and CP

Design-Technology Co-optimization for Stacked Nanosheet Oxide Channel Transistors in Monolithic 3D Integrated Circuit Design

Design-Technology Co-optimization for Stacked Nanosheet Oxide Channel Transistors in Monolithic 3D Integrated Circuit Design

Toward Reliability- and Variability-Aware Design-Technology Co-Optimization in Advanced Nodes: Defect Characterization, Industry-Friendly Modeling, and ML-Assisted Prediction

Toward Reliability- and Variability-Aware Design-Technology Co-Optimization in Advanced Nodes: Defect Characterization, Industry-Friendly Modeling, and ML-Assisted Prediction

Design–technology co-optimization for 2D electronics

Design–technology co-optimization for 2D electronics

Modeling of microtrenching and bowing effects in nanoscale Si inductively coupled plasma etching process

Plasma etching effects, such as microtrenching and bowing, negatively impact device performance. Modeling of these effects at nanoscale is challenging, and theoretical and experimental investigations are highly desired to gain insights into mechanisms. In this paper, we propose a new plasma etching model based on Monte Carlo simulations with a cellular method. This model considers reactions and ion-enhanced etching and consists of a novel particle reflection algorithm, which is a key factor impacting the etch profile. This model reproduces the adjustable microtrenching and bowing effects in periodic dense trenches with tens of nanometer dimensions. We conduct experiments of Si etching by Cl2 and validate the model by comparing the simulated profile with cross-sectional scanning electron microscope images. This work enables a potential physical model driven process emulation tool toward design technology co-optimization.

DTCO optimizes critical path nets to improve chip performance with timing-aware OPC in deep ultraviolet lithography.

Design technology co-optimization (DTCO) is a potential approach to tackle the escalating expenses and complexities associated with pitch scaling. This strategy offers a promising solution by minimizing the required design dimensions and mitigating the pitch scaling trend. It is worth noting that lithography has played a significant role in dimensional scaling over time. This paper proposes a DTCO flow to reduce the impact of the process variation (PV) band and edge placement error (EPE). First, we performed the digital back-end design of the high-performance processor and got the test layout; second, we executed timing analysis on the test layout to get the critical path net that affects the chip performance; third, we proposed the timing-aware optimized optical proximity correction (OPC) method to optimize the PV band and EPE by adjusting the weights of critical path net merit points, optimizing the generation of the sub-resolution assistant feature, giving tighter EPE specs for merit points on the critical path net, and placing denser merit points as well as denser breakpoints for the critical path net to obtain greater freedom in the OPC process. Finally, it is verified that our proposed DTCO process can significantly reduce the EPE and lead to a slight decrease in the PV band of the chip while maintaining the same process windows.

(Invited) Strategies for Characterization and Parameter Extraction of Vertical Junction-Less Nanowire FETs Dedicated to Design Technology Co-Optimization

In the era of emerging computing paradigms and artificial neural networks, hardware and functionality requirements are in the surge. In order to meet low power and latency criteria, new architectures for in-memory computing are being explored as alternatives to traditional von Neumann machines, which requires technological breakthrough at the semiconductor device level such as vertical gate-all-around junctionless nanowire field effect transistors (VNWFET), that can address many process challenges such as downscaling, short-channel effects, compactness and electrostatic control. Its integration in the mainstream design flow is not straightforward and requires design technology co-optimization (DTCO) at an early stage. This invited paper explores strategies for accurate characterization and parameter extraction of the VNWFETs to feed the DTCO compact models [1].As an important first step to access the intrinsic device characteristics, one must remove or ‘de-embed’ the parasitic contributions of external test structures and interconnections. However, for technologies such as the 3D VNWFET, precision of the S-parameter de-embedding step is crucial for accurate model parameter extraction. On the current fabricated VNWFET wafer, only open structures were available and the standard open de-embedding method led to inaccurate or even unphysical values of intrinsic capacitances. While one could design and fabricate additional de-embedding test structures to overcome this, to avoid another design cycle, a new dedicated de-embedding method was developed based on the modelling of the transistor interconnects, leveraging EM simulation [2]. After accurately calibrating the EM simulation against S-parameter measurements of the Open structure, virtual test structures of the same technological process, layout and material properties, were designed in the EM simulation environment. This included Open and Short structures at different reference planes that were simulated for extracting individual interconnect parasitic contributions. Next, the EM simulation served as a predictive tool to construct an electrical equivalent circuit of the entire 3D VNWFET interconnection network (Fig.1). Compared with conventional de-embedding techniques based on Open and Short measurements, the proposed interconnect network modelling-based approach relies on fewer test structures and can provide better accuracy, necessary for compact model parameter extraction.The DTCO is driven by the use of VNWFETs in highly compact 3D logic circuits. Design of these logic circuits relies heavily on compact models, containing a set of physics-based analytical equations for the juntionless transistors. The compact model developed for the 18 nm VNWFET technology [3] has been extensively validated against measurements depicting very good agreement over the entire bias range. To leverage the model for predictive design through DTCO, we further explored the scalability for all available transistor geometries that showed a visible improvement in current scalability for larger devices (Fig.2). However, process variation has limited linear current scaling in smaller nanowire diameters that are of more interest for junctionless transistor operation. In contrast, for a given number of parallel nanowires, maintaining gate electrostatic control over the channel in larger diameters becomes more difficult along with a degradation of the drain current on/off ratio, despite better current scaling (Fig.3). So as a design trade-off for the DTCO, we chose transistors with an optimal diameter (where junctionless functionality and gate electrostatic control are maintained for individual nanowires) with a higher number of nanowires in parallel to boost the drive current.Reliability assessment through electro-thermal measurements of VNWFETs is crucial when designing 3D logic circuits within DTCO framework, particularly for evaluating long-term performances and underlying transport mechanisms. Conventional methods for thermal investigation were not applicable for the VNWFETs as the drain current shows steady increase with temperature in contrast with classical devices (Fig.4). Since activation of self-heating could not be confirmed using traditional methods, a new methodology for thermal resistance estimation in VNWFETs is developed. This relies on the intersecting points on ID-VG curves at different measurement temperatures (TA) and power dissipations (Pdiss) corresponding to same VG and ID. From the ratio of junction temperatures (Tj=TA+RTH*Pdiss) for the two sets of intersecting curves related to different VD and threshold voltages and subsequent calculations, thermal resistances (RTH) were extracted. Theoretical calculations corroborated extracted results with RTH values ranging between 4 and 28×104 K/W. Other non-conventional methods were also explored such as low-frequency S-parameter measurements or RTH extraction using the slope of drain current versus temperature plot at different dissipated powers, all of which offered similar results even though measurement uncertainties related to each method should be carefully accounted for. A final verification using full device thermal simulation in COMSOL multiphysics, accounting for both ballistic and diffusive heat flux, showed fair agreement with experimental results. This is the first demonstration of thermal resistance extraction in highly-scaled VNWFETs. Figure 1

On the SRAM with comb-shaped nano FETs advancing to 3 nm node and beyond

In this paper, we describe several scaling challenges of SRAM consisting of FinFETs and horizontal Gate-All-Around (GAA) Nano-sheet Field-Effect-Transistors (NshFETs), especially investigations related to Design-Technology Co-Optimization (DTCO). Comb-shaped channel FETs (CombFETs), which integrates the advantages of FinFETs and NshFETs were introduced to a six-transistor (6 T) SRAM cell and the corresponding simulations were established. The results show that compared with both FinFETs and NshFETs, CombFETs have larger the effective channel width or higher current at the same footprint and larger room for improving the mobility mismatch between N/P transistors. Moreover, CombFET SRAM showed ∼55% increase in effective channel width, 15% improvement of read static noise margin, ∼25% write speed gain, 88% read speed gain or 20% decrease in the minimum operating voltage (Vmin).

Design Technology Co-Optimization Strategy for Ge Fraction in SiGe Channel of SGOI FinFET.

FinFET devices and Silicon-On-Insulator (SOI) devices are two mainstream technical routes after the planar MOSFET reached the limit for scaling. The SOI FinFET devices combine the benefits of FinFET and SOI devices, which can be further boosted by SiGe channels. In this work, we develop an optimizing strategy of the Ge fraction in SiGe Channels of SGOI FinFET devices. The simulation results of ring oscillator (RO) circuits and SRAM cells reveal that altering the Ge fraction can improve the performance and power of different circuits for different applications.

(Invited) Strategies for Characterization and Parameter Extraction of Vertical Junction-Less Nanowire FETs Dedicated to Design Technology Co-Optimization

In the era of emerging computing paradigms and artificial neural networks, hardware and functionality requirements are in the surge. In order to meet low power and latency criteria, new architectures for in-memory computing are being explored as alternatives to traditional von Neumann machines, which requires technological breakthrough at the semiconductor device level such as vertical gate-all-around junctionless nanowire field effect transistors (VNWFET), that can address many process challenges such as downscaling, short-channel effects, compactness and electrostatic control. Its integration in the mainstream design flow is not straightforward and requires design technology co-optimization (DTCO) at an early stage. This invited paper explores strategies for accurate characterization and parameter extraction of the VNWFETs to feed the compact models allowing DTCO-efficient strategies.

A Process-Aware Compact Model for GIDL-Assisted Erase Optimization of 3-D V-NAND Flash Memory

This article presents the accurate compact modeling methodology to optimize the gate-induced drain leakage (GIDL)-assisted erase operation for vertical stack-up, multiple stack, and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Z</i> -directional shrink of the 3-D vertically integrated NAND (V-NAND) flash memory. The artificial neural network (ANN) is initially applied in the V-NAND transistors to describe the various GIDL characteristics with channel profile variations. In addition, physics-based <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> network models are investigated to accurately model the complex process in the state-of-the-art V-NAND products. All models are implemented in Verilog-A, and the time dynamics of the GIDL-assisted channel potential increase for erase operations are successfully reproduced in the SPICE simulations. This SPICE-compatible compact model is essential to the design technology co-optimization (DTCO) for over 200-layer V-NAND, because the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> delay-related erase failures have become an important issue in the high aspect ratio (HAR) channel holes. Based on the proposed compact model, the highly accurate GIDL-assisted erase simulations are performed, and an erase optimization procedure is demonstrated with GIDL injection level, physical etch limit, and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Z</i> shrink rate in the next V-NAND candidate structures. Therefore, this process-aware compact model is a valuable tool for pathfinding activities in the early stage of 3-D V-NAND flash memory development.

Impact Study of Layout-Dependent Effects Toward FinFET Combinational Standard Cell Optimization

With the increased device integration density in advanced semiconductor technologies, the layout-dependent effects (LDEs) have become critical affecting both device-level and circuit-level performance. In this brief, we report an impact study of LDEs on 14-nm FinFET combinational standard cells to facilitate the process of design-technology co-optimization (DTCO). Focusing on the poly pitch, cut poly effect, oxide spacing effect, and cell height, improvement in speed and power consumption of typical 14-nm FinFET combinational standard cells has been achieved. Seven standard cell libraries are further designed and constructed based on the LDE study, enabling comprehensive applications with different performance, power and area (PPA) preference. Such DTCO and demonstrated experimental results can be attractive in future customized designs employing the enriched standard cell libraries at advanced technology nodes.

Fast and Expandable ANN-Based Compact Model and Parameter Extraction for Emerging Transistors

In this paper, we present a fast and expandable artificial neural network (ANN)-based compact model and parameter extraction flow to replace the existing complicated compact model implementation and model parameter extraction (MPE) method. In addition to nanosheet FETs (NSFETs), our published ANN-based compact modeling framework is easily extended to negative capacitance NSFETs (NC-NSFETs), which are attracting attention as next-generation devices. Each device is designed using a technology computer-aided design (TCAD) simulator. Using device structure parameters, temperature, and channel doping depth as input variables, we construct a dataset of electrical properties used for machine learning (ML)-based modeling. The accuracy of predicting device electrical characteristics with the proposed ANN-based compact model is less than a 1% error compared to TCAD, and simulation results of digital and analog circuits using the proposed compact model show less than a 3% error. This allows the ANN-based modeling framework to achieve accurate DC, AC, and transient simulations without restrictions on device technology. In particular, temperature and process variables such as channel doping depth, which are not defined in the compact model parameters, are easily added to the previously presented five key parameters. Instead of conventional complex compact modeling and MPE work, we propose a method to create fast, accurate, flexible, and expandable ML-based Verilog-A SPICE models with design technology co-optimization (DTCO) capabilities.