Impact Study of Layout-Dependent Effects Toward FinFET Combinational Standard Cell Optimization

Abstract

With the increased device integration density in advanced semiconductor technologies, the layout-dependent effects (LDEs) have become critical affecting both device-level and circuit-level performance. In this brief, we report an impact study of LDEs on 14-nm FinFET combinational standard cells to facilitate the process of design-technology co-optimization (DTCO). Focusing on the poly pitch, cut poly effect, oxide spacing effect, and cell height, improvement in speed and power consumption of typical 14-nm FinFET combinational standard cells has been achieved. Seven standard cell libraries are further designed and constructed based on the LDE study, enabling comprehensive applications with different performance, power and area (PPA) preference. Such DTCO and demonstrated experimental results can be attractive in future customized designs employing the enriched standard cell libraries at advanced technology nodes.