Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning

Abstract

As technology nodes evolve, geometric pitch scaling starts to slow down. In order to retain the trend of the Moore's Law, Design Technology Co-Optimization (DTCO) and System Technology Co-Optimization (STCO) are introduced together to continue scaling beyond 5nm using pitch scaling, patterning, and novel 3D cell structures (i.e., Complementary-FET (CFET)). However, numerous DTCO and STCO iterations are needed to continue block-level area scaling with considerations of cost, various standard cell (SDC) heights, SDC architectures, design rules, and back end of line (BEOL) settings. The growing turnaround time (TAT) among standard cell design, design rule optimization, and block-level area evaluation becomes one of the major bottlenecks in DTCO and STCO explorations. In this work, we propose a DTCO and STCO sensitivity prediction method to improve the performance of DTCO and STCO explorations on block-level area using machine learning techniques. We study and extract the key metrics of block-level designs, SDCs, design rules, and BEOLs. We use a machine learning model to predict the sensitivity of minimum valid block-level area when tuning the design rules and BEOLs with various SDC sets (i.e., different cell heights, Conventional FET, CFET, etc.). We firstly demonstrate that the proposed model achieves 4.05 ×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−3</sup> mean absolute error (MAE) for testing sets to predict block-level area sensitivity of various SDC sets, design rules, and BEOL settings. Then, we show that the proposed model successfully captures the block-level area sensitivity of new SDC sets and new BEOL settings across multiple SDC sets and designs with 3.3 ×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> and 6 ×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−3</sup> MAEs, respectively. Lastly, the proposed modeling approach achieves 5.75 ×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−2</sup> MAE on average in the robustness experiment on predicting new designs. The proposed framework provides more than 100× speedups compared to conventional DTCO and STCO exploration flows.