Design Space Exploration Method Research Articles

A Fast Performance Estimation Framework for System-Level Design Space Exploration

This paper presents a fast performance estimation framework and an performance estimation method for design space exploration at system level. As the complexity of embedded systems grows, design space exploration at a system level plays a more important role than before. In the system-level design, system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various Processing Elements (PEs) including processors and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. In order to shorten the evaluation time, we have developed a fast design space exploration framework which combines our system-level design tool, named SystemBuilder, and a newly developed fast performance estimation tool, named SystemPerfEst. SystemPerfEst is based on trace-based simulation method. The trace is obtained as the result of SystemBuilder, and the trace is fed to SystemPerfEst smoothly. Since the estimation of a design candidate finishes in about one second, design space exploration of a number of design candidates can be performed with SystemPerfEst in a practical time. A case study on design space exploration of a JPEG decoder system demonstrates the effectiveness of our framework.

Machine learning predictive modelling high-level synthesis design space exploration

A machine learning-based predictive model design space exploration (DSE) method for high-level synthesis (HLS) is presented. The method creates a predictive model for a training set until a given error threshold is reached and then continues with the exploration using the predictive model avoiding time-consuming synthesis and simulations of new configurations. Results show that the authors' method is on average 1.92 times faster than a genetic-algorithm DSE method generating comparable results, whereas it achieves better results when constraining the DSE runtime. When compared with a previously developed simulated annealer (SA)-based method, the proposed method is on average 2.09 faster, although again achieving comparable results.

A model-driven engineering framework for embedded systems design

This work presents a Model-Driven Engineering (MDE) framework to improve embedded system design. The framework adopts concepts from MDE for the automatic generation of a control and data flow internal representation, starting from the functional specification of an embedded application described using UML class and sequence diagrams. By means of transformations rules applied on the UML model of the embedded system, an MOF-based (Meta Object Facility is a standard representation for meta-models and models proposed by OMG) internal representation is automatically obtained, which is iteratively mapped into a hardware/software implementation by means of model transformations. This mapping is optimized by a design space exploration (DSE) method based on a categorical graph product. The model transformations have also as input a platform model, which specifies the available hardware, software and interface resources, and produce an implementation model, on which software synthesis, communication synthesis and high-level synthesis algorithms are applied to generate the final implementation. A case study is described to illustrate the application of the framework.

A Fast Design Space Exploration Method for Reconfigurable Architecture Based on Loop Optimization

Using FPGA for general-purpose computation has become a hot research topic in high-performance computing technologies. However, the complexity of design and resource of FPGA make applying a common approach to solve the problem with mixed constraints impossible. Aiming at familiar loop structure of the applications, a design space exploration method based on FPGA hardware constrains is proposed according to the FPGA chip features, which combines the features of the corresponding application to perform loop optimization for reducing the demand of memory. Experimental results show that the method significantly improves the rate of data reuse, reduces the times of external memory access, achieves parallel execution of multiple pipelining, and effectively improves the performance of applications implemented on FPGA.

Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design

We present a hardware sharing method for design space exploration of multi-processor embedded systems. In our prior work, we had developed a system-level design tool named SystemBuilder which automatically synthesizes target implementation of a system from a functional description. In this work, we have extended SystemBuilder so that it can automatically synthesize an area-efficient implementation which shares a hardware module among different applications. With SystemBuilder, designers only need to enable an option in order to share a hardware module. The designers, therefore, can easily explore a design space including hardware sharing in short time. A case study shows the effectiveness of the hardware sharing on design space exploration.

A networks-on-chip architecture design space exploration – The LIB

Many on-chip network circuit and architecture techniques are incompatible with modern design flows, making them unsuitable for use in systems-on-chip. This paper presents a networks-on-chip (NoC) architecture design space exploration method for multi-processor systems-on-chip architecture. The NoC architecture design space is designed with a Layer-Interactive-Building block (LIB) methodology that is divided into three layers: application layer, link/network layer, and physical layer. The suggested LIB design paradigmatic philosophy provides modular building block structure in both hardware and software and the protocols for their interconnection in the three architecture layers. Using LIB the designer can easily select these building blocks to build application-specific NoCs to meet different application requirements such as media, graphic, software radio and communication network applications. The LIB provides the NoC building blocks, architecture interacting systems-on-chip components, the programming models and application mapping strategies. The LIB can be used as a complementary library and tools for future on-chip interconnection network design.

Exploration de l'espace de conception des architectures reconfigurables

During many years, the designers just had two possibilities to design embedded systems; microprocessors and/or application specific integrated circuits. Nevertheless, a new possibility has appeared lately, the reconfigurable circuits. These systems have an important lack of tools at all design levels. Designers are then facing the difficult task of designing their target reconfigurable architectures, which is a critical issue since it can strongly affect the final system performances. To help them in that task, it is necessary to develop tools that enable an efficient design space exploration. With such tools, designers could improve synergy between application and architecture and then choose the best one for their application. In this article, we propose a design space exploration method for reconfigurable architectures dedicated to data intensive applications. The design space exploration takes place at the first stages of the design flow before any architectural definition. MOTS-CLES : Architecture des systemes reconfigurables, Estimation haut niveau des performances, Exploration de l'espace de conception.

An Iterative Method for Algorithms Implementation on a Limited Dynamically Reconfigurable Hardware

In this study we propose a framework and a combined temporal partitioning and design space exploration method for run time reconfigurable processors. Our objective is to help designers to implement an algorithm in limited FPGA area resources while respecting the execution time constraint. The algorithm to be implemented is represented by a task graph with different implementation alternatives (design points) for each task. We study the effect of hardware resources limitation in the choice of the algorithm implementation design point. The proposed method is based on an heuristic technique which consists on combining temporal partitioning and task design points selection to obtain solutions that satisfy the imposed constraints.

Constraints-driven design space exploration for distributed embedded systems

This paper presents a new method for design space exploration for distributed embedded systems. The method is based on constraint logic programming (CLP) and make it possible to model distributed embedded systems and design requirements using finite domain constraints. Design space exploration tools can then use this model to find different solutions satisfying constraints. An advantage of this method is its flexibility to defined design constraints and ability to mix both manual design decisions and automatic optimization methods. The solution of the set of constraints provides a final system implementation which, by definition, satisfies all imposed design constraints. Both algorithms guaranteeing optimal solutions and heuristic methods can be used in the optimization phase.

Scheduling techniques for variable voltage low power designs

This paper presents an integer linear programming (ILP) model and a heuristic for the variable voltage scheduling problem. We present the variable voltage scheduling techniques that consider in turn timing constraints alone, resource constraints alone, and timing and resource constraints together for design space exploration. Experimental results show that our heuristic produces results competitive with those of the ILP method in a fraction of the run-time. The results also show that a wide range of design alternatives can be generated using our design space exploration method. Using different cost/delay combinations, power consumption in a single design can differ by as much as a factor of 6 when using mixed 3.3V and 5V supply voltages.