True Random Number Generator Design Research Articles

Entropy Computation for Oscillator-based Physical Random Number Generators

In this paper, we provide a complete set of algorithms aimed at the design and security evaluation of oscillator-based True Random Number Generators (TRNG). While depending on some TRNG design assumptions, the proposed algorithms use as inputs the statistical parameters of the underlying random physical process such as the clock jitter originating from the thermal noise and give a lower bound of the entropy rate of the generated bit stream as output. We describe the general structure of a TRNG composed of multiple free-running oscillators and samplers, the outputs of which are post-processed by an entropy conditioner. Depending on the specification of the entropy conditioner, which can usually be any Boolean function, we describe several algorithmic optimizations. We then explain how to compute and efficiently manage the entropy rate at the output of such a post-processing block and at the output of the generator as a whole.

High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator

Unpredictable true random numbers are required in security technology fields such as information encryption, key generation, mask generation for anti-side-channel analysis, algorithm initialization, and so on. At present, the true random number generator (TRNG) is not enough to provide fast random bits by low-speed bits generation. Therefore, it is necessary to design a faster TRNG. This work presents an ultra-compact TRNG with high throughput based on a novel extendable dual-ring oscillator (DRO). Owing to multiple bits output per cycle in DRO can be used to obtain the original random sequence, the proposed DRO achieves a maximum resource utilization to build a more efficient TRNG, compared with the conventional TRNG system based on ring oscillator (RO), which only has a single output and needs to build multiple groups of ring oscillators. TRNG based on the 2-bit DRO and its 8-bit derivative structure has been verified on Xilinx Artix-7 and Kintex-7 FPGA under the automatic layout and routing and has achieved a throughput of 550 Mbps and 1,100 Mbps, respectively. Moreover, in terms of throughput performance over operating frequency, hardware consumption, and entropy, the proposed scheme has obvious advantages. Finally, the generated sequences show good randomness in the test of NIST SP800-22 and Dieharder test suite and pass the entropy estimation test kit NIST SP800-90B and AIS-31.

A 2.5 pJ/bit PVT-Tolerant True Random Number Generator Based on Native-NMOS-Regulated Ring Oscillator

In this brief, an energy-efficient true random number generator (TRNG) is presented based on the jitter noise of a single ring oscillator (RO). By XORing two different oscillation stages of the RO, consecutive pulses can be generated due to the fixed intrinsic propagation delay and more importantly, the time-varying jitter-noise-caused variation to the above delay. By continuously quantizing the above pulses’ width using another high-frequency RO-based time-to-digital converter (TDC), the TDC’s least significant bits (LSBs) are dominated by the jitter noise, of which the magnitude can be largely increased through reducing the RO’s supply voltage with a native NMOS transistor. Based on a 40-nm standard CMOS process, the proposed TRNG design is fabricated and extensively characterized. By passing the widely-exploited test tools of National Institute of Standards and Technology (NIST) and autocorrelation function, the proposed TRNG’s randomness has been well validated. Moreover, the randomness evaluation is further extended to various process-voltage-temperature (PVT) conditions, and the measured Shannon entropy is always larger than 0.999995, showing excellent PVT tolerance. Finally, the proposed TRNG features a high energy efficiency of 2.5 pJ/bit at a throughput of 53 Mbps.

Optimizing free layer of Magnetic Tunnel Junction for true random number generator

True random number generators (TRNGs) should ideally generate lengthy chains of non-repeating, uncorrelated bit-streams that are efficient in terms of both energy and area. Current TRNG designs include source of randomness such as CMOS or non-volatile memory based devices with additional circuitry to improve the quality of randomness leading to power and area overhead. This paper addresses these issues by improving the randomness of the Spin-Orbit Torque (SOT)-Magnetic Tunnel Junction cell. Motivated by the observation that free layer thickness of Magnetic Tunnel Junction (MTJ) can be scaled to design a low-barrier device, the paper proposes a novel source of randomness called ΔSOT. This device is then used to design TRNG circuits that achieves high quality random telegraphic switching behavior without any additional circuitry making it suitable for ultra-low power applications. Evaluations show that ΔSOT-TRNG has significant reduction in energy (51%) and area (66%) compared to state-of-the-art MTJ based TRNG design. Furthermore, the work shows that the improved switching speed of the reduced barrier junction can results in 65% increase in throughput compared to MTJ based TRNG design.

Birds of the Same Feather Flock Together: A Dual-Mode Circuit Candidate for Strong PUF-TRNG Functionalities

Physically Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) are two highly useful hardware primitives to build up the root-of-trust for embedded devices in Internet-of-Things and Cyber-Physical System applications. These applications demand the primitives be lightweight, yet flexible. However, PUFs are designed to offer <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">repetitive and instance-specific</i> randomness, whereas TRNGs are expected to be <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">invariably</i> random. A challenging but thought-provoking problem from a hardware designer's perspective would be to design a circuit that serves the purpose of both PUF and TRNG depending on the exact requirement of the application. Here, we present a dual-mode PUF-TRNG design that utilises two different hardware-intrinsic properties, i.e. oscillatory metastability of Transition Effect Ring Oscillator (TERO) cell and propagation delay of a buffer within the cell to achieve this goal. A 48.62% reduction in area is accomplished due to the integration in comparison to separate instances of standalone PUFs/ TRNG designs, built from Programmable Delay Line (PDL) based Arbiter PUFs (APUFs) and TERO-TRNG. Our final design has a hardware footprint of 618 Look-Up Tables (LUTs) and 447 Flip-Flops (FFs). Furthermore, experimental analysis of the state-of-the-art modelling attacks, reliability attacks on the proposed PUF design shows a prediction accuracy of 55.37% and 50.14% respectively for 5.2M Challenge Response Pairs (CRPs). Additionally, the TRNG passes evaluation through National Institute of Standards and Technology (NIST) Special Publication (SP) 800-22 and German Federal Office for Information Security (BSI) Application Notes and Interpretation of the Scheme (AIS)-31 tests.

Jitter-based Adaptive True Random Number Generation Circuits for FPGAs in the Cloud

In this article, we present and evaluate a true random number generator (TRNG) design that is compatible with the restrictions imposed by cloud-based Field Programmable Gate Array (FPGA) providers such as Amazon Web Services (AWS) EC2 F1. Because cloud FPGA providers disallow the ring oscillator circuits that conventionally generate TRNG entropy, our design is oscillator-free and uses clock jitter as its entropy source. The clock jitter is harvested with a time-to-digital converter (TDC) and a controllable delay line that is continuously tuned to compensate for process, voltage, and temperature variations. After describing the design, we present and validate a stochastic model that conservatively quantifies its worst-case entropy. We deploy and model the design in the cloud on 60 EC2 F1 FPGA instances to ensure sufficient randomness is captured. TRNG entropy is further validated using NIST test suites, and experiments are performed to understand how the TRNG responds to on-die power attacks that disturb the FPGA supply voltage in the vicinity of the TRNG. After introducing and validating our basic TRNG design, we introduce and validate a new variant that uses four instances of a linkable sampling module to increase the entropy per sample and improve throughput. The new variant improves throughput by 250% at a modest 17% increase in CLB count.

Next generation QCA technology based true random number generator for cryptographic applications

The penchant for almost all modern-day devices is high data and communication security. To achieve the highest standard of security, hardware-based encryption architectures like true random number generators (TRNG) and physically unclonable functions (PUF) supersede attack deterrence to any known software-based cryptography algorithm. The keys generated are random and unpredictable. This paper proposes a new architecture for TRNG in quantum-dot cellular automata (QCA) technology using feedback and feed-forward D flip-flop arrangement with small delay defects. A new optimized negative edge-triggered D flip-flop is presented using only 25-QCA cells. This unique and carefully curated TRNG structure ensures the generated output bits are highly unpredictable and truly random in behavior. Furthermore, 15 statistical tests designed for random number generators are performed. These test results validate the random nature of the generated outputs and unpredictable behavior of the proposed TRNG design. The energy dissipation analysis shows a significant improvement of 49.6% for energy dissipation per bit compared to existing designs.

FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter

This article describes about the design, implementation, and analysis of a true random number generator (TRNG) employing an all-digital phase-locked loop (ADPLL) based on a finite impulse response (FIR) filter as the digital loop filter and implemented on the Artix 7(XC7A35T-CPG236-1) field programmable gate array (FPGA) board using the Xilinx Vivado v.2015.2 design suite. The coefficients of a 3rd-order broadcast low-pass digital FIR filter are computed using the Keiser window method. The MATLAB-FDA tool is used to calculate the filter coefficient. After reducing the bias in the sequence using the XOR-corrector post-processing approach, the suggested ADPLL-based TRNG designs created an unbiased stochastic random number with an overall throughput of 200 Mbps for both designs. The first proposed FIR-ADPLL-based TRNG design (FAT-1) consumes 0.072 W of power, whereas the second proposed FIR-ADPLL-based TRNG design (FAT-2) consumes 0.074 W. The resulting bitstream is verified for randomness using national institute of standards and technology (NIST) test following post-processing. Digital storage oscilloscope (DSO) is interfaced to the Artrix-7 FPGA board in order to capture the TRNG output waveforms. Both the proposed FIR-based ADPLL-TRNG designs passed the NIST SP 800-22 test, indicating that they are well-suited for a variety of industrial applications, including network security, cybersecurity, banking security, smart cards, radio-frequency identification tags, Internet of Things, and Industrial Internet of Things.

A Unified PUF and TRNG Design Based on 40-nm RRAM With High Entropy and Robustness for IoT Security

Physically unclonable function (PUF) and true random number generator (TRNG) are the indispensable primitives for the Internet-of-Things (IoT) security. In this article, a highly robust unified PUF<inline-formula> <tex-math notation="LaTeX">$/$ </tex-math></inline-formula>TRNG design is demonstrated. An entropy source (ES) chip based on 40-nm resistive random access memory (RRAM) is designed and fabricated, and a pseudo-forming technique is developed to ensure excellent robustness. The unified PUF<inline-formula> <tex-math notation="LaTeX">$/$ </tex-math></inline-formula>TRNG is tested across <inline-formula> <tex-math notation="LaTeX">$- 55\,\,^{\circ }\text{C}$ </tex-math></inline-formula> to 125 &#x00B0;C with different supply voltages, achieving &#x003C; 0.001&#x0025; bit error rate (BER) and &#x003E;0.999 worst case min-entropy simultaneously. Excellent randomness is verified by NIST SP800-22 and 90B tests. This highly robust unified design can implement an authentication system with the authentication error rate (AER) approaching 0&#x0025; and thus is promising for future IoT security applications.

A New Energy-Efficient and High Throughput Two-Phase Multi-Bit per Cycle Ring Oscillator-Based True Random Number Generator

Oscillator-based elementary true random number generator (TRNG) uses a slow jittery ring oscillator (RO) to sample a fast RO. The ROs are always on but most of the oscillatory cycles of the fast RO are not sampled into random bits. In this paper, a new lightweight TRNG design is proposed to minimize the power wasted by the superfluous oscillations. Random bits are extracted from both phases of the slow ROs to increase the throughput and the fast RO is activated only during the narrow transition time difference between two symmetrically designed slow ROs. The slow jittery ROs are implemented using current starved inverters biased in the weak inversion region to reduce their power consumption. Their jitter amplitudes are increased by lowering the oscillation frequency and reducing the drain current of the transistors. The narrow jittery pulse generated by the differential pair of slow ROs is quantized by the fastest three-stage RO. Two random bits from each phase of the jittery ROs can be extracted by using a gigahertz dynamic toggled D flip-flop counter to count the number of oscillatory cycles of the fast RO. The proposed TRNG is fabricated in a standard 65 nm 1.2 V CMOS process. Measurement results of the fabricated chips show that the proposed TRNG consumes merely <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$260~\mu \text{W}$ </tex-math></inline-formula> at a bit rate of 52 Mbps. It outperforms the state-of-art on-chip jitter-based TRNGs with the best figure-of-merit of 5 pJ/bit and the smallest footprint of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$366~\mu \text{m}^{2}$ </tex-math></inline-formula> . Its generated bit sequence passes the statistical randomness tests including National Institute of Standards and Technology (NIST) test, Auto Correlation Factor (ACF) test and bias. The mean redundancy of the ten tested chips is measured to be less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−5</sup> bit/symbol.

Design and Synchronization of Chaos-Based True Random Number Generators and Its FPGA Implementation

In this paper, a new chaos-based true random number generator (TRNG) and a sliding mode controller (SMC) to synchronize the proposed TRNGs are proposed. Firstly, the continuous chaotic system is transformed into a discrete system that preserves the original continuous system’s chaotic behavior and makes it easy to realize with the field-programmable gate array (FPGA) for synchronization control. Then, a discrete SMC is introduced to solve the synchronization problem of the master-slave discrete chaotic systems. Subsequently, a novel hybrid function integrated with the El-Gamal algorithm is proposed to complete the TRNG design. Finally, the FPGA-based realization of the synchronized master-slave TRNGs is implemented. The randomness quality of the proposed TRNGs has been ensured by using Shannon’s entropy and histogram analysis. Furthermore, the National Institute of Standards and Technology (NIST) test suite has also been introduced to evaluate the proposed TRNGs and compare with the existing results in the literature.

Pure Digital Scalable Mixed Entropy Separation Structure for Physical Unclonable Function and True Random Number Generator

This study presents a pure digital scalable mixed entropy separation structure for the physical unclonable function (PUF) and true random number generator (TRNG), which is implemented on Xilinx field-programmable gate arrays (FPGAs). The mixed entropy separation structure in this study is to solve the problems of unstable output in the existing PUF structure and the poor scalability of the TRNG and PUF design. The proposed design has the following innovations: 1) concept of sensitive entropy and the corresponding processing method are proposed for the first time; 2) design does not need to modify the internal design of the entropy source, and it is suitable for most entropy source arrays; and 3) adjustable PUF bit width and TRNG throughput enhance the scalability of the architecture under different requirements. The structure is simulated and validated on two Xilinx FPGAs and tested under nominal working conditions. The results show that the 512-bit PUF entropy source after treatment is 92.7% more stable than the 1024-bit entropy source before treatment, the random number after treatment passes all types of randomness tests, and the minimum entropy is more than 0.8. Under various conditions within the ranges of 0 °C–80 °C and 0.8–1.2 V, the TRNG output remains stable after treatment; the maximum intra-Hamming distance of the treated PUF is 5.1028%, and the average intra-Hamming distance is 2.7065%.

Design of True Random Number Generator Using Fingerprint as an Entropy Source and Its Implementation in S-Box

This paper deals with the design of a true random number generator (TRNG) using the fingerprint as an entropy source and its implementation in substitution box (S-box) of Advanced Encryption Standard (AES). Considering fingerprint as a unique and random arrangement of minutiae, these minutiae points are used as the source of entropy. The proposed design utilizes fewer resources minimizing hardware redundancy and enhancing the level of randomness. This TRNG has been designed and validated using Artix-7 FPGA. The data rate, speed and latency have been obtained as 40 Mbps, 5 Mbps and 305 ns, respectively. The generated random bit stream had also been sampled and converted to a binary format in MATLAB and tested through the National Institute of Standards and Technology (NIST) 800.22 statistical suite for validation. The proposed TRNG design pass efficiency achieved is more than 95% for a sample size of 10 binary sequences.

Design and Analysis of Configurable Ring Oscillators for True Random Number Generation Based on Coherent Sampling

True Random Number Generators (TRNGs) are indispensable in modern cryptosystems. Unfortunately, to guarantee high entropy of the generated numbers, many TRNG designs require a complex implementation procedure, often involving manual placement and routing. In this work, we introduce, analyse, and compare three dynamic calibration mechanisms for the COherent Sampling ring Oscillator based TRNG: GateVar , WireVar , and LUTVar , enabling easy integration of the entropy source into complex systems. The TRNG setup procedure automatically selects a configuration that guarantees the security requirements. In the experiments, we show that two out of the three proposed mechanisms are capable of assuring correct TRNG operation even when an automatic placement is carried out and when the design is ported to another Field-Programmable Gate Array (FPGA) family. We generated random bits on both a Xilinx Spartan 7 and a Microsemi SmartFusion2 implementation that, without post processing, passed the AIS-31 statistical tests at a throughput of 4.65 Mbit/s and 1.47 Mbit/s, respectively.

Tunnel FET‐based ultra‐lightweight reconfigurable TRNG and PUF design for resource‐constrained internet of things

SummaryConventional complementary metal oxide semiconductor (CMOS)‐based dedicated true random number generator (TRNG) and physically unclonable function (PUF) designs have exhibited higher energy consumption and large area overhead with technology scaling. In contrast, this paper for the first time presents emerging tunnel field‐effect transistor (TFET)‐based ultra‐lightweight reconfigurable TRNG and PUF design. A unique methodology is proposed that considers p‐i‐n forward current characteristics to generate random keys for PUF and TRNG designs. Leveraging the p‐i‐n forward current of TFET, a ring oscillator (RO) is designed that exhibits variation in the operating frequency and acts as the main source of entropy for both PUF and TRNG. The TRNG in the proposed design is robust and passed all the National Institute of Standards and Technology (NIST) tests. Considering the variation in p‐i‐n forward current, the uniqueness of PUF is calculated as 47.5% and 46% at a supply voltage of 0.5 and 0.45 V, respectively. Moreover, PUF achieves high reliability of 82% and 88.7% with supply voltage and temperature variations, respectively. The proposed design is proved to be compact with relatively lower gate count and shows low energy consumption of 4.8 pJ/bit at 0.5‐V supply voltage. With these performance metrics, the proposed design is highly suitable for resource‐constrained internet of things (IoT).

A Novel Dormand-Prince Based Hybrid Chaotic True Random Number Generator on FPGA

This study presents a novel Dormand-Prince-based hybrid chaotic True Random Number Generator Design (TRNG) that can be used for secure communication and cryptographic applications on Field Programmable Gate Array (FPGA). In this design, a chaotic oscillator unit has been implemented with an FPGA-based Sprott-Jafari chaotic oscillator model suitable with IQ-Math fixed point number and IEEE 754-1985 floating point number standards. Random numbers have been produced with the quantization of the results generated by the chaotic oscillator. XOR has been performed with FPGA-based ring oscillator structure on the post-processing unit so as to enhance the randomness. The differential equation of the chaotic system used in the TRNG design was modelled using Dormand-Prince numerical algorithm method. The design on FPGA has been realized in two separate number formats including 32-bit (16I-16Q) IQ-Math fixed point number standard and 32-bit IEEE 754-1985 floating point number standard. The realized designs have been coded in VHDL, a hardware description language, and the Xilinx ISE 14.7 program has been used for the system design. Two separate TRNG designs have been synthesized and tested for the Virtex-6 (XC6VLX240T-1FF1156) FPGA chip. The maximum operating frequency of the TRNG with 32-bit IQ-Math fixed point number standard is 344.585 MHz and the throughput is approximately 344 Mbit/s. The maximum operating frequency of the TRNG with 32-bit IEEE 754-1985 floating point number standard is 316.756 MHz and the throughput is 316 Mbit/s. 1 Mbit sequence has been generated by both designed TRNG systems. Randomness analysis of the generated numbers has been performed in accordance with the NIST 800-22 tests and the generated numbers have successfully passed all of the tests.

Improved Performance of SRAM-Based True Random Number Generator by Leveraging Irradiation Exposure.

Encryption is an important step for secure data transmission, and a true random number generator (TRNG) is a key building block in many encryption algorithms. Static random-access memory (SRAM) chips can be easily available sources of true random numbers, benefiting from noisy SRAM cells whose start-up values flip between different power-on cycles. Embarking from this phenomenon, a novel performance (i.e., randomness and throughput) improvement method of SRAM-based TRNG is proposed, and its implementation can be divided into two phases: irradiation exposure and hardware postprocessing. As the randomness of original SRAM power-on values is fairly low, ionization irradiation is utilized to enhance its randomness, and the min-entropy can increase from about 0.03 to above 0.7 in the total ionizing irradiation (TID) experiments. Additionally, while the data remanence effect hampers obtaining random bitstreams with high speed, the ionization irradiation can also weaken this impact and improve the throughput of TRNG. In the hardware postprocessing stage, Secure Hash Algorithm 256 (SHA-256) is implemented on a Field Programmable Gate Array (FPGA) with clock frequency of 200 MHz. It can generate National Institute of Standards and Technology (NIST) SP 800-22 compatible true random bitstreams with throughput of 178 Mbps utilizing SRAM chip with 1 Mbit memory capacity. Furthermore, according to different application scenarios, the throughput can be widely scalable by adjusting clock frequency and SRAM memory capacity, which makes the novel TRNG design applicable for various Internet of Things (IOT) devices.

0.4 mW, 0.27 pJ/bit true random number generator using jitter, metastability and current starved topology

This study introduces the design of true random number generator (TRNG) using jitter, metastability and current starved topology. The proposed design consisted of a current starved inverter-based ring oscillator (RO) with a high-frequency divider block (designed by T-FF followed by D-FF to address setup and hold time issues), jitter extraction and metastable block followed by two sampling blocks. The design avails fewer amenities to yield the reduction in hardware and enhances the degree of randomness. The post-layout simulation of the proposed work was performed using a 180 nm CMOS technology environment in the Cadence Virtuoso tool. The speed and power dissipation achieved are 1.5 Gbps and 0.4 mW, respectively, with an efficiency of 0.27 pJ/bit. The effect of temperature and variation in supply voltages (by 10% around its nominal value) is also investigated on the generated random numbers through parametric analysis. For validation of randomness, the generated random signals are first sampled and then converted in binary format using MATLAB and finally verified by Kolmogorov–Smirnov and Chi-square test for the uniformity and independency. The validity of the proposed work is done by NIST 800.22 statistical test suite. The proposed TRNG design achieved a very high-pass efficiency.

A High-Performance and Secure TRNG Based on Chaotic Cellular Automata Topology

As an important hardware security primitive, the true random number generator (TRNG) has been widely utilized in many critical applications. The performance and security of TRNGs are always dominant features that determine the usability of a TRNG scheme. In this article, we propose a novel TRNG design method based on a self-timed ring structure. Different from most existing self-timed circuit-based TRNGs that use ring oscillators, the basic circuit component of the proposed TRNG is a digital realization of a chaotic cellular automata topology. We utilize three different methods to validate the proposed TRNG method, including HSpice simulation, FPGA prototype, and ASIC test chips. As the proposed TRNG structure is pure digital, thus it is synthesizable with standard all-digital components. The test chips of the proposed TRNG structure are fabricated with 40 nm TSMC technology node, with a hardware footprint equals to 75 NAND gates and a die area of 270 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . With a PCIe setup connecting the testchip and computer, the TRNGs achieves high throughput as 1600 Mb/s. The FPGA implementation is built on a Virtex6 family FPGA from Xilinx, which also achieves lightweight overhead: 53 look-up-table (LUT) and 22 D Flip-flops (DFF). The collected random numbers from FPGA implementations and ASIC testchips are comprehensively tested with three test suites, including NIST SP800-22, NIST SP800-90B, and AIS-31 with a high pass-rate. Further, the security of the TRNG testchips and FPGA implementations are validated by applying three different attacks, including frequency injection attacks, power attacks, and thermal attacks. The experimental results demonstrate that the proposed TRNG structure is immune to these attacks with trivial entropy loss.

A Compact Low-Voltage True Random Number Generator Based on Inkjet Printing Technology

Printed electronics (PE) is a fast-growing field with promising applications in wearables, smart sensors, and smart cards, since it provides mechanical flexibility, and low-cost, on-demand, and customizable fabrication. To secure the operation of these applications, true random number generators (TRNGs) are required to generate unpredictable bits for cryptographic functions and padding. However, since the additive fabrication process of the PE circuits results in high intrinsic variations due to the random dispersion of the printed inks on the substrate, constructing a printed TRNG is challenging. In this article, we exploit the additive customizable fabrication feature of inkjet printing to design a TRNG based on electrolyte-gated field-effect transistors (EGFETs). We also propose a printed resistor tuning flow for the TRNG circuit to mitigate the overall process variation of the TRNG so that the generated bits are mostly based on the random noise in the circuit, providing a true random behavior. The simulation results show that the overall process variation of the TRNGs is mitigated by 110 times, and the generated bitstream of the tuned TRNGs passes the National Institute of Standards and Technology - Statistical Test Suite. For the proof of concept, the proposed TRNG circuit was fabricated and tuned. The characterization results of the tuned TRNGs prove that the TRNGs generate random bitstreams at the supply voltage of down to 0.5 V. Hence, the proposed TRNG design is suitable to secure low-power applications in this domain.