Design Of Thin Film Transistors Research Articles

P‐1.6: Design of High Charge Gain Oxide TFTs Based Active Pixel Sensing Circuit

Dynamic X‐ray detecting for large area medical imaging requires high‐gain and stable Active Pixel Sensor (APS) circuit integrated with Thin Film Transistors (TFTs). In this paper, the APS circuit using oxide TFTs is studied based on the small‐signal model, and the charge gain and effects of threshold voltage shift (ΔVth) are investigated. Detailed SPICE simulations show the charge gain of the APS circuit of the oxide TFTs is 234 × of that of the conventional a‐Si:H TFT PPS circuit.

Effect of Hydrogen on Long-Term Reliability of InZnO TFTs Characterized by Low-Frequency Noise

The long-term reliability of InZnO (IZO) thin film transistors (TFTs) under a hydrogen-containing environment is researched. Hydrogen incorporation induces hydroxyl groups and oxygen vacancies, leading to the generation of electrons and extra random trap/emission processes in the IZO films. Consequently, the electrical properties and low frequency noise characteristics of IZO TFTs are deteriorated under the long-term hydrogen treatment. Additionally, the recovery characteristics of IZO TFTs after the hydrogen treatment demonstrate that the hydrogen induced hydroxyl groups and oxygen vacancies remain stable at room temperature. The oxygen vacancies can be eliminated, while the hydroxyl groups may still exist at a high temperature. These results may provide useful guidelines in the design and application of IZO TFTs.

Deep Subthreshold TFT Operation and Design Window for Analog Gain Stages

The intrinsic gain ( ${\mathrm{ A}}_{\mathrm{ i}}$ ), transconductance efficiency ( ${\mathrm{ g}}_{\mathrm{ m}}/{\mathrm{ I}}_{\mathrm{ DS}}$ ) and cut-off frequency ( ${\mathrm{ f}}_{\mathrm{ T}}$ ) are analysed for thin film transistors (TFTs) operating in the deep subthreshold region to assess the impact of device variations on the design window for analogue circuits. Results suggest that subthreshold operation could improve the $\text{A}_{\mathrm{ i}}$ and ${\mathrm{ g}}_{\mathrm{ m}}/{\mathrm{ I}}_{\mathrm{ DS}}$ at the cost of reduced ${\mathrm{ f}}_{\mathrm{ T}}$ and increased sensitivity to bias and process variations. Interestingly, a less steep subthreshold slope (SS) could, to some extent, compensate for these shortcomings, which is in contrast to the general thinking of pursuing a steeper SS in TFT fabrication.

Review of recent advances in flexible oxide semiconductor thin-film transistors

ABSTRACTThis paper describes the recent advances in flexible oxide thin-film transistors (TFTs), one of the rapidly emerging technologies for the next-generation display applications. First, the paper focuses on the effect of the buffer layer over the plastic substrate, which significantly influences the electrical performance and stability of oxide TFTs. Then oxide semiconductor TFTs fabricated through atomic layer deposition among the various oxide semiconductor fabrication methods were reviewed due to their potential as high-performance flexible TFTs. Finally, the mechanical fatigue behaviors of the TFTs were investigated, including the various mechanical factors, such as the bending radius, cycles, and stress directions. Structural solutions for the TFT were also introduced, such as TFT design modification and the use of the neutral plane concept, to improve the mechanical durability.

A Carbon Nanotube Electrode a-IGZO-TFT

In this paper, amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) using carbon nanotubes (CNTs) as source/drain/gate electrodes have been proposed and experimentally realized. Effect of the annealing temperature on the contact properties between a-IGZO and single-walled carbon nanotube (SWNT) electrodes, as well as the electrical properties of the a-IGZO TFTs have been investigated. The contact performance between SWNT electrodes and a-IGZO active layer has been improved by increasing the annealing temperature. The resulting a-IGZO TFT with SWNT electrodes shows an effective mobility of 8 cm2/ $\text{V}\cdot {\mathrm{ s}}$ and an on/off current ratio of $1.9\times 10^{7}$ under a drain voltage of 10 V. This SWNT-electrode a-IGZO TFT design makes it possible for CNTs as electrodes of the metal oxide TFT.

Rational Design of ZnO:H/ZnO Bilayer Structure for High-Performance Thin-Film Transistors.

The intriguing properties of zinc oxide-based semiconductors are being extensively studied as they are attractive alternatives to current silicon-based semiconductors for applications in transparent and flexible electronics. Although they have promising properties, significant improvements on performance and electrical reliability of ZnO-based thin film transistors (TFTs) should be achieved before they can be applied widely in practical applications. This work demonstrates a rational and elegant design of TFT, composed of poly crystalline ZnO:H/ZnO bilayer structure without using other metal elements for doping. The field-effect mobility and gate bias stability of the bilayer structured devices have been improved. In this device structure, the hydrogenated ultrathin ZnO:H active layer (∼3 nm) could provide suitable carrier concentration and decrease the interface trap density, while thick pure-ZnO layer could control channel conductance. Based on this novel structure, a high field-effect mobility of 42.6 cm(2) V(-1) s(-1), a high on/off current ratio of 10(8) and a small subthreshold swing of 0.13 V dec(-1) have been achieved. Additionally, the bias stress stability of the bilayer structured devices is enhanced compared to the simple single channel layer ZnO device. These results suggest that the bilayer ZnO:H/ZnO TFTs have a great potential for low-cost thin-film electronics.

Intrinsic Channel Mobility of Amorphous, In–Ga–Zn–O Thin-Film Transistors by a Gated Four-Probe Method

Intrinsic mobility and intrinsic channel resistance $(R_{\rm CH})$ of amorphous, In–Ga–Zn–O (a-IGZO) thin-film transistors (TFTs) with varying channel length $(L)$ are investigated using a gated four-probe back-channel-etched TFT design. The intrinsic $R_{\rm CH}$ is found to decrease from ${\sim}{500}$ to ${\sim}{\rm 250}~{\rm k}\Omega$ per unit area by increasing $V_{\rm GS}$ from 10 to 20 V. The intrinsic mobility is ${\sim}{\rm 17}~{\rm cm}^{2}/{\rm V}\cdot{\rm s}$ , which is about 20% higher than that derived from the normal two-point probe measurements. Source and drain parasitic resistance $(R_{\rm PAR})$ of the a-IGZO TFTs is found to be of the same order of magnitude as the $R_{\rm CH}$ —which is different from hydrogenated amorphous-silicon (a-Si:H) TFTs, where TFT operation is dominated by $R_{\rm PAR}$ .

Edge Effects in Bottom-Gate Inverted Staggered Thin-Film Transistors

For thin-film transistor (TFT) characterization and simulation, accurate knowledge of the effective channel width ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$W_{\rm EFF}$</tex></formula> ) and effective channel length ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$L_{\rm EFF}$</tex></formula> ) is required, particularly in narrow and/or short devices, where small dimensional variations may result in large overestimation/underestimation of device parameters. Although a substantial amount of research has been done to determine <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$L_{\rm EFF}$</tex></formula> , there is very little work presented regarding <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$W_{\rm EFF}$</tex></formula> . Here, we report a design-related existence of current leakage paths along the channel edges in inverted staggered TFT structures. Applied here for the case of amorphous-silicon- and amorphous-oxide-semiconductor-based TFTs, a model is developed to investigate the edge effect from a series of TFTs with various channel widths ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$W$</tex></formula> ). <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$W_{\rm EFF}$</tex></formula> is found to be larger than the designed <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$W$ </tex></formula> , resulting in an overestimation of the extracted TFT parameters such as the field-effect mobility. It is concluded that a preferred TFT design consists of source and drain electrodes that extend over the active area along the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$W$</tex></formula> direction to minimize the edge effects and, hence, improve the accuracy of the extracted TFT parameters.

Critical issues in plasma deposition of microcrystalline silicon for thin film transistors

After more than 20 years of research and despite improved transport properties with respect to amorphous silicon, microcrystalline silicon thin film transistors (TFTs) are not yet ready for industrial production. We review here the progress made in the understanding of the growth of this material with particular emphasis on industry relevant aspects such as deposition rate and uniformity. We show that the synthesis of silicon nanocrystals in the plasma offers unique advantages with respect to deposition rate and film properties. In particular, this allows the production of films which are similar to polycrystalline thin films produced by furnace and laser crystallization. The growth process is also discussed with respect to TFT design: top gate or bottom gate. Results on bottom gate TFTs meeting all the necessary requirements in terms of mobility, ON/OFF ratio and stability required for AMOLED applications are also reported.

Method for the determination of bulk and interface density of states in thin-film transistors

In this article we present a method for the accurate determination of interface and bulk density of states (DOS) in thin-film transistors (TFTs), based on the combined analysis of transfer (ID–VGS) and capacitance–voltage characteristics. This analysis has achieved a number of results, eliminating sources of inaccuracies that are known to be present in other methods. A procedure for the determination of the electron and hole flatband conductances and bulk Fermi energy is demonstrated. A recursive procedure is employed to extract the bulk DOS directly from Poisson’s equation. The advantages of this method are the greater immunity to noise from the original data, the use of the complete Fermi function (no 0 K approximation), and the applicability to thin active layers. This method yields the interface state density spectrum as well as the bulk DOS. This information is very important for device design, process characterization, and modeling of TFTs.

Determination of the surface potential in thin-film transistors from C–V measurements

In this article we present a method for the determination of the gate voltage versus surface potential (VGS−ψS) relationship in thin-film transistors (TFTs), from low frequency capacitance–voltage (C–V) characteristics. This information is very important for device design, process characterization, and modeling of TFTs and provides the basis for extracting the gap density of states. The accuracy of the method is demonstrated by applying it to the analysis of C–V data generated by two-dimensional simulations. Its application to laser recrystallized polysilicon TFTs is presented.

1/f noise in pentacene organic thin film transistors

We report on the flicker (1/f ) noise in pentacene organic thin film transistors (TFTs) of different designs. Our studies show that the TFT design affects the noise level and the noise dependence on the gate- and drain-source biases. The measured noise level was the lowest for the TFTs with a top source and drain contacts design. For these devices, the noise dependence at low drain current values resembled that for n-type crystalline Si metal–oxide–semiconductor field-effect transistors. The extracted Hooge parameter α, which allows comparing the noise level in different devices and materials, was 0.045 for the top-contact TFTs. This parameter value is several orders of magnitude lower than that for conducting polymers and only several times higher than that for hydrogenated amorphous Si (α-Si:H) TFTs. The bottom source and drain contacts TFTs had a much higher noise level with a noise dependence on the terminal voltages that differed from the noise voltage dependence for the top-contact TFTs. The Hooge parameter values were in the range of 5–20 for the bottom-contact TFTs. We estimated that the contact noise could be comparable to the channel noise for both top-contact and bottom-contact TFTs.

Electrical Instabilities and 1/f Noise in Organic Pentacene Thin Film Transistors

ABSTRACTWe report on the influence of Bias-Temperature Stress (BTS) on the pentacene Thin Film Transistors (TFTs) electrical characteristics and on their 1/f noise level. The gate BTS primarily affects the TFT threshold voltage, leaving both mobility and sub-threshold slope values almost unchanged. The degree of the threshold voltage shift induced by the positive or negative BTS depends on the TFT design and the BTS parameters. The current-voltage characteristics time dependence of the organic TFTs, subjected to the BTS, resembles that for amorphous-Si TFTs. The results of the 1/f noise measurements in the organic TFTs allowed us to conclude that the gate BTS primarily affects the TFT contact regions, resulting in the increase of both the contact noise and the contact resistance.