Design Of Semiconductor Devices Research Articles

Levelized incomplete LU method and its application to semiconductor device simulation

In circuit simulation, the CPU time is spent in two parts: one is to transfer the circuit equation into the corresponding linear equation Ax= B, the other is to solve this matrix equation. In order to improve the simulation speed and apply our method to mixed-level device and circuit simulation, we propose to simplify the creation of the matrix equation by equivalent subcircuit, and speed up the simulation by levelized incomplete LU factorization [Karl-Michael E, Walter LE. IEEE Trans Comp Aided Des Integ Circ and Sys 1995;14:720.]. The levelized incomplete LU is used to solve Ax= B because it offers, the good convergence of the direct method and the high speed, small memory space of the iteration method. The Ax= B is obtained by transferring the Poisson equation and continuity equation into their equivalent circuits [Leblebici Y, Unlu MS, Morkoc H, Kang SM. IEEE Int Symp Circ and Sys 1992;2:895; 1995;13:396.] to simplify the mixed-level simulation. Finally, we will apply the above methods to the simulation of PN diodes and verify their performance on the simulation and design of semiconductor devices.

An Optimization Approach to a Finite Dimensional Parameter Estimation Problem in Semiconductor Device Design

In this paper the parameter selection in semiconductor device design is posed as an optimization problem: given an ideal voltage-current (V-I) characteristic, find one or more physical and geometrical parameters such that the V-I characteristic of the device matches the ideal one optimally with respect to a prescribed performance criterion. The voltage-current characteristic of a semiconductor device is governed by a set of nonlinear partial differential equations (PDE), and thus a black-box approach is taken for the numerical solution of the PDEs. Various existing numerical methods are proposed for the solution of the nonlinear optimization problem. The Jacobian of the cost function is ill-conditioned and a scaling technique is thus proposed to stabilize the resulting linear system. Numerical experiments, performed to show the usefulness of this approach, demonstrate that the approach always gives optimal or near-optimal solutions to the test problems in both two and three dimensions.

Refractive index measurements of ZnSe-based ternary epitaxial layers grown by molecular-beam epitaxy on GaAs (100)

ZnSe-based II–VI ternary alloys, such as ZnBeSe, ZnMgSe, and ZnCdSe, have been shown to be excellent candidates for light-emitting device applications in the short-wavelength visible range. Since design of optical semiconductor devices requires knowledge of refractive indices of all materials involved, we studied refractive indices of Zn1−xBexSe, Zn1−xMgxSe, and Zn1−xCdxSe epitaxial layers. The samples were grown by molecular-beam epitaxy in mole fractions ranges between 0⩽x⩽0.81, 0⩽x⩽0.59, and 0⩽x⩽0.57 for Zn1−xBexSe, Zn1−xMgxSe, and Zn1−xCdxSe, respectively. The alloy concentration x was determined by x-ray diffraction. All samples exhibited very high crystalline quality, even at relatively high values of x. A prism-to-film coupler technique, which involves optical tunneling via evanescent fields, was employed to accurately determine the indices of refraction. The variation of the refractive index with alloy composition at room temperature was determined at the wavelength of 632.8 nm.

Homoepitaxial Diamond Devices

AbstractDiamond has been proposed as an excellent material for high‐temperature, high‐power, and high‐frequency applications. The interest in diamond electronics is due to its large electric breakdown field, high‐saturated current velocity and high‐thermal conductivity. As silicon and gallium arsenide devices begin to reach their performance limits, there is a need to develop new, better performing materials such as diamond. Significant progress in the development of diamond as a semiconducting material has been made and diamond has been implemented into numerous conventional and novel device designs. In this work homoepitaxial diamond material properties and device performance are reviewed. In summary, the large activation energy of boron‐doped p‐type diamond and phosphorus‐doped n‐type diamond severely limits diamond's use in conventional semiconductor device designs. The large activation energy reduces the number of charge carriers, which limits the current handling capability and produces temperature‐dependent device performance. To overcome diamond's limitations, novel devices, such as enhancement mode field effect transistors (FETs) that use a hydrogenated surface conducting layer or pulsed doped devices with almost complete ionization, have been investigated. These devices require further development. The initial results show promise for high‐temperature, high‐frequency, and high‐power applications.

Design for semiconductor manufacturing. Bibliography

Interest in integrating the design and manufacture of semiconductor devices has been growing over the past decade. Often referred to as design for manufacture (DFM), integrated product development seeks to conceive and refine design alternatives that make the best use of manufacturing capabilities, in terms of the various materials, processes, tools, equipment, and facilities available to realize the design. While there is a large and growing literature on DFM generally, comparatively little of the published work addresses design for semiconductor manufacturing (DFSM) specifically, or the unique technologies and special circumstances of the semiconductor industry. In this paper, we present the results of a DFSM literature and software survey undertaken during the period June 1995 through August 1996. We describe the methods and sources used in the survey and include the complete abstracts of 61 articles determined to be most significant for DFSM. Also included is listing and brief description of some related software packages, which are available commercially or by anonymous ftp from a number of World Wide Web sites.

Design for semiconductor manufacturing. Perspective

The semiconductor industry is challenged to sustain the historical rate of exponential growth in product innovation and productivity for as long into the future as possible. If this challenge is to be met, substantial investments in chip-design automation are required to improve design capabilities and to narrow the widening gap between projected increases in device complexity and design productivity. Design for manufacture (DFM) is one potential means to leverage the required investment in design automation. DFM focuses on understanding how the design of a product interacts with the various processes and facilities available to make that product, in order to conceive and refine design alternatives that tend to optimize the product in the context of existing or projected manufacturing capabilities. In this paper, we review the current literature on DFM as applied in other industries and consider the relevance of state-of-the-art DFM principles and tools to improved efficiency and productivity within the semiconductor industry. We observe that, overall, many of the organizational structures for implementing DFM already exist within semiconductor firms and the industry more broadly. Moreover, much of the existing spectrum of layout, modeling, simulation, and analysis tools used for semiconductor device, process, equipment, and factory design can be thought of as components of a de facto system of design for semiconductor manufacturing (DFSM). While recent work aimed specifically at DFSM shows great promise, advances in the development of component design tools are lagging and integration of these tools into a coherent system for DFSM is only emerging. Systems integration of tools which characterize future processes and technologies will be needed in order to posit design rules which are sufficiently robust to allow their incorporation in industry-standard automated design and layout tools. The implications are that there is a need for accelerated improvements in DFSM tools and integration if historical semiconductor productivity growth is to be sustained.

Dielectric function and reflectivity of 3C–silicon carbide and the component perpendicular to the c axis of 6H–silicon carbide in the energy region 1.5–9.5 eV

The optical properties of commercially available 3C- and 6H-SiC single crystals were studied in the energy region 1.5–9.5 eV with conventional and synchrotron-radiation spectroscopic ellipsometry. The surface perfection of the materials was investigated by transmission electron and atomic force microscopies. The calculated values for the effective and static dielectric functions were higher than those found in the literature. This is consistent with the fine structure and absolute values of the corresponding reflectance spectra, which were higher than those reported in other studies. The dispersion of the refractive indices in the energy region below and above the indirect gap is determined and can be used as reference and for the design and analysis of semiconductor structures and devices.

The use of semantic networks to support concurrent engineering in semiconductor product development

The design of semiconductor devices is an extremely complex and costly process. Numerous design and test iterations are typically necessary to finally complete a successful device. Competition in the industry has forced semiconductor manufacturers to reduce design cycle times and costs. One method now being used to accomplish these objectives is concurrent engineering. This paper will review how concurrent engineering is being integrated into semiconductor device development and how artificial intelligence-based models will support concurrent engineering implementation. Major changes are needed in design simulation, methods of knowledge sharing, and incorporating best practices. A semantic network is proposed that retains the knowledge of a product in a central repository as various engineers contribute to the product's development. The knowledge contained in this central repository can be referenced for applicability by engineers during product design, development, and production.

Bandgap engineering of semiconductor heterostructures by molecular beam epitaxy: physics and applications

Bandgap engineering is a powerful technique for the design of new semiconductor materials and devices. Heterojunctions and molecular beam epitaxy allow band diagrams with nearly arbitrary and continuous bandgap variations to be made. In this way the transport and optical properties of these artificially structured semiconductors can be tailored at will. Interesting new phenomena have been discovered in these materials and a new generation of devices with unique capabilities is emerging from this approach. Finally, the tunability of band discontinuities via doping interface dipoles is discussed.

The electromagnetic behaviors of a large object under high power microwave environment (abstract)

In order to investigate the behavior of aerospace asserts exposed to high power microwaves (HPM) or electromagnetic pulse (EMP) modeling the time-dependent electromagnetic (EM) behavior of the flying body before or after actual experiments has received significant attentions. The present available finite-difference time-domain method have fundamental difficulties in meeting the needs when the object has either complex geometry (including complex composite materials) or large physical size. We have proposed a method which can overcome the above-mentioned difficulties in EM modeling. The method is based upon a card-shuffle parallel algorithm used on a massive parallel computer. The initial test has been carried out on several types of computers. It enhances the modeling ability significantly. To model a large size flying body under HPM environment is no longer an impossible thing. The method can also provide effective approach to deal with many other important applications whenever it involves solving a wavelike equation and demanding giant computer storage. Examples are antenna design, aerodynamics, upset and damage model of semiconductor devices, turbulence, neural network, etc. Further improving the method is ongoing.

THE INFLUENCE OF LATTICE HEATING ON SEMICONDUCTOR DEVICE CHARACTERISTICS

Self‐consistent electrothermal simulation of modern semiconductor devices is required for the accurate and efficient design and optimization of many semiconductor devices. The need to perform this type analysis in order to predict the behavior of power devices was realized many years ago. It is now clear that nonisothermal analysis can be very important for VLSI devices as well.

Bandgap and interface engineering for advanced electronic and photonic devices

Bandgap engineering is a powerful technique for the design of new semiconductor materials and devices. Heterojunctions and modern growth techniques, such as molecular beam epitaxy, allow band diagrams with nearly arbitrary and continuous bandgap variations to be made. The transport properties of electrons and holes can be tuned independently and continuously for a given application. A new generation of devices with unique capabilities, ranging from solid-state photomultipliers to resonant-tunneling transistors, is emerging from this approach. Finally, the tunability of band discontinuities via doping interface dipoles is discussed.

Use of the three-dimensional TLM method in the thermal simulation and design of semiconductor devices

The thermal behavior of semiconductor devices fabricated with a variety of different materials has been analyzed using the three-dimensional transmission-line matrix (TLM) method. This method can easily incorporate the temperature dependence of thermal parameters, is numerically stable, and compares favorably with other numerical techniques in computational expenditure and convenience in modeling complex geometries. As an example, a three-dimensional thermal analysis of a typical microwave power device structure is presented. The model demonstrates the effects of overlay metal and conductivity of the substrate material in limiting the temperature rise. Both the transient and steady-state thermal operation are quantitatively studied. The study shows that the TLM method has considerable potential in the thermal analysis and design of semiconductor devices. >

Boundary Element Heat Conduction and Thermoelastic Analyses of Interface Crack in LSI Package in Consideration of Contact Between Crack Surfaces.

The interface crack initiated between the die pad (lead frame) and the resin encapsulant in the LSI package sometimes leads to package cracking and becomes critical to package fracture design. On the other hand, the property of thermal diffusion has become a main concern for recent package design of power semiconductor devices. To simulate these problems, we developed the boundary element heat conduction and thermoelastic analysis code, which can deal with thermoelastic contact of the interface crack. The stress intensity factors for an interface crack are calculated by the extrapolation method which is proposed by one of the authors. Using the above technique, the interface crack initiated in a plastic-molded LSI package is analyzed under conditions of uniform temperature loading and heat generation in the Si-chip. Calculated interfacial stress intensity factor Ki shows a decreasing trend against the interface crack length in all the above cases. Taking into account the contact of the crack surface, the results of the disturbance in temperature distribution are outstanding. However, the normalized stress intensity factor Ki/|ΔTmax| Shows almost identical behavior against with the crack length and is less dependent on the contact region length and the amount of heat generation.

Heterojunction band discontinuities and tunable band offsets: building blocks for bandgap engineering

The bandgap engineering approach is reviewed, and its applications to the design of advanced semiconductor devices are discussed. The tunability of band offsets using delta doping interface dipoles is also described in light of recent experimental and theoretical developments.

Microstructural evaluation of reactive ion etched - regrown GaAs

Reactive ion etching (RIE) is a preferred dry process step for fabrication of submicron III-V semiconductor device structures. This kinetically assisted chemical dry etch process offers several important advantages over other etching methods, namely etch anisotropy, etch rate control, selectively, accuracy, uniformity across the wafer and reproducibility. As a result of these desirable characteristics, a number of semiconductor device designs involve REE in their device fabrication process. Some of the more novel designs involve lateral quantum well arrays, whereby fabrication requires molecular beam epitaxial (MBE) regrowth on RIE semiconductors.A major drawback of RIE is the potential lattice damage introduced by energetic ion bombardment and contamination. This material damage may lead to deterioration of device performance. It is important to identify and understand this RIE induced damage in order to develop and refine the RIE process, i.e. minimize crystal damage and thus optimize device performance. This study identifies and analyzes the damage associated with various RIE parameters used for quantum well fabrication. Microstructural characterization via TEM is used to identify the nature of lattice defects, their distribution, and density. Optical methods, Photoluminescence and Raman spectroscopy are used to evaluate the crystal damage and serve as a reliable comparators for the TEM results.

The use of simulation in semiconductor technology development

An overview is presented on the types of problems encountered in semiconductor technology development that are actively studied today via simulation methods. Most of the simulation examples presented here are ones that have been explicitly used in actual industrial semiconductor device design cycles to aid in the optimization of device structures. The examples described here include process simulations, such as the diffusion of dopant atoms, oxidation, etching, deposition, and epitaxial growth, as well as device simulations, which predict the flow of charge carriers and field distribution within a semiconductor device, given its material structure and operating conditions. The main aim here is to illustrate, by example, some of the capabilities of state-of-the-art simulators used in characterizing and predicting semiconductor process and device-related phenomena. We will attempt to outline the degree of sophistication of the physics incorporated in such simulation programs, and provide some contrast to the fundamental physics required for a complete physical description. As will be indicated, simulation development necessarily involves molding the appropriate physical models and numerical algorithms into a package that can be handled in a reasonable length of time by modern computing systems. We briefly outline some of the advances that have been made, and some concerns that remain, in such simulation development.

Analysis and design of semiconductor devices using strain

Abstract A brief review of the use of hydrostatic pressure to studies of group IV and group III-V semiconductor systems and devices is given. The internal loss mechanisms in semiconductor lasers designed for optical fibre communications are identified using hydrostatic pressure and suggestions made how inbuilt strain in quantum-well and superlattice structures may be used to fabricate much improved devices. The critical hot carrier transitions in silicon and in germanium avalanche photodiodes are examined using hydrostatic pressure and again possible improvements in strained Si, Ge and SiGe alloys are suggested.

Design and comparison of advanced semiconductor devices using computer experiments: application to APDs and HEMTs

A computer experimental procedure that is useful for studying the behavior of advanced semiconductor devices that contain nonlinear effects is discussed. The approach draws on previous work in modeling avalanche photodiodes (APDs) and high-electron-mobility transistors (HEMTs) based on an ensemble Monte Carlo model. An overall approach to modeling these devices that emphasizes the built-in controls and the importance of bootstrapping the model is presented. The approach is not limited only to APDs and HEMTs, however, because virtually any semiconductor device can be successfully modeled following this procedure. As a means of illustrating the usefulness of this technique, previous device calculations are reviewed and new results are presented. Computer experiments that either compare the performances of different device designs or permit the optimization of an existing structure are presented. Specifically, the optimal operating point of a GaAs/AlGaAs-doped quantum-well APD is bracketed. >

Measurement of Relaxation in Strained Layer Semiconductor Structures

Many advanced semiconductor device designs require the growth of heteroepitaxial layers with lattice parameters differing by up to a few percent with respect to the substrate. X-ray diffraction offers a nondestructive method of determining the extent of relaxation. This paper discusses the sensitivity of x-ray techniques to small amounts of relaxation, describes how relaxation is measured in cubic materials for layer on (001) substrates and suggests nomenclature for the case of asymmetric relaxation.