Parallel Multiplier Design Research Articles

CMOS High-Performance 5-2 and 6-2 Compressors for High-Speed Parallel Multipliers

In this article, the design fashion of high-speed 5-2 and 6-2 compressors along with their analysis, has been discussed. With the help of combinational logic consisting of the 4-2 compressor and 3-2 counter structures, a high-performance structure for 6-2 compressor has been obtained which shows significant speed improvement over previous architectures. The optimization is achieved by reducing the carry rippling issue between adjacent compressor blocks. Also, the proposed 6-2 compressor with some modifications will turn into a 5-2 compressor in which latency of the critical path has considerably been reduced, illustrating the superiority of designed circuits. The delay of proposed 5-2 and 6-2 structures is equal to 3.5 and 4 XOR logic gates, respectively, demonstrating speed boosting of 15% and 20% compared to the best-reported architectures. In addition, the power consumption and transistor count of proposed circuits are in reasonable level. Therefore, by considering the Power-Delay Product (PDP), our work will be a good choice for high-speed parallel multiplier design. Post-layout simulation results based on TSMC 90nm standard CMOS process and 0.9V power supply have been presented to confirm the correct functionality of the implemented compressors. These results have also been used as a fair comparison infrastructure between the proposed works and redesignated architectures of previously reported schemes.

Novel Booth Encoder and Decoder for Parallel Multiplier Design

Novel Booth Encoder and Decoder for Parallel Multiplier Design

Low-power parallel multiplier with column bypassing

A low-power parallel multiplier design, in which some columns in the multiplier array can be turned-off whenever their outputs are known, is proposed. This design maintains the original array structure without introducing extra boundary cells, as was the case in previous designs. Experimental results show that it saves 10% of power for random input. Higher power reduction can be achieved if the operands contain more 0's than 1's.

High-speed Booth encoded parallel multiplier design

This paper presents a design methodology for high-speed Booth encoded parallel multiplier. For partial product generation, we propose a new modified Booth encoding (MBE) scheme to improve the performance of traditional MBE schemes. For final addition, a new algorithm is developed to construct multiple-level conditional-sum adder (MLCSMA). The proposed algorithm can optimize final adder according to the given cell properties and input delay profile. Compared with a binary tree-based conditional-sum adder, the speed performance improvement is up to 25 percent. On average, the design developed herein reduces the total delay by 8 percent for parallel multiplier. The whole design has been verified by gate level simulation.

AN ADIABATIC 4:2 COMPRESSOR DESIGN FOR LOW POWER VLSI

4:2 compressors are basic components in the design of parallel multipliers. Low power consuming 4:2 compressors can result in a significant reduction of power when realizing power-efficient multipliers in any low power oriented systems. In the area of low power integrated circuit design, adiabatic switching technique has received considerable attention in the recent years. Many adiabatic logic architectures have been reported. In this letter, a low power 4:2 compressor circuit based on the adiabatic switching principle is proposed. When simulated using HSPICE, it was shown that the proposed circuit consumed very much less power than the static CMOS version.

New parallel multiplier design

A new parallel multiplier structure is proposed. In this multiplier the operands are partitioned into four groups of bits to produce 16 partial product terms. The novelty of the new structure is that these partial product terms are each repartioned further into two groups. This will enable the use of parallel counters rather than carry lookahead adders in the intermediate stages. It is shown that the proposed technique has better performance than existing designs with respect to both area and speed.

Design and analysis of VLSI-based parallel multipliers

A design of a parallel multiplier is presented in which the time-consuming multiplication process is recursively decomposed into simple summation processes that can be executed simultaneously. At each recursive step, each multiplier and multiplicand is partitioned into four groups of bits and produces 16 partial product terms. An efficient summation process of adding up these partial product terms is proposed. These terms are grouped in accordance with their relative bit positions and with the use of three-to-two counters. Based on the proposed summation process, the multiplier can achieve a speed complexity of order O(log2n). Owing to its regular structure, the proposed parallel multiplier is feasible for VLSI implementation. In the paper, the designs of parallel multipliers implementing various orders of partitions are also studied. The results show that partitioning each multiplier and multiplicand into five groups of bits can generally yield a higher speed performance with less chip area for arbitrary bit size.

A single chip parallel multiplier by MOS technology

A parallel multiplier design based on the five-counter cell is discussed. A design optimization for the performance in speed is proposed at the logic design level which is developed into an MOS circuit design. The comparison of the five-counter cell design and the full adder cell design reveals that the proposed design is most useful with pass gate logic and results in high-speed multiplication (approximately twice as fast as that of the full adder design) with a moderate increase in hardware complexity. With the five-counter design, an improvement in the hardware complexity of a squarer can be expected. >