Design Of Logic Circuits Research Articles

A Novel Method for Designing Electronic Logic Circuits

This scientific paper presents a novel method for designing single and multi-output electronic logic circuits. The produced circuit consists of two parts. The first part consists of (n-1) XOR gates, where "n" is the number of input signals to the logic circuits. This part is called the linear part of the circuit. The second part is designed by any method used in designing logic circuits. This part called the non-linear part of the circuit. The suggested method can be programmed by any high level programming language to be used on any digital computer especially with the circuits which have a large number of input signals.

Thermal Characterization Methodologies for Experimental Minichannel Heat Sink Designs in Printed Circuit Board Assemblies

There has been a growing demand for novel, highly efficient, power-saving cooling solutions in recent years. In many cases, standard cooling techniques offer only limited opportunities to prevent the overheating of circuits. Such issues concern high-speed Printed Circuit Board Assemblies (PCBA) in data centers and telecommunication racks, where the flow of the cooling medium is obstructed due to the lack of space. Size limitations can also be a serious problem when cooling high-power devices because the devices consume a large space. Since the heat sink-based cooling solutions and the sophisticated IC packages only deal with one possible heat flow path, we were given the idea of enhancing the secondary heat flow path towards the Printed Circuit Board (PCB). Led by this intention, the idea of creating an embedded minichannel system inside the circuit board and circulating the cooling agent was realized. Through this method, we could decrease the board-to-ambient thermal resistance significantly. This paper presents the demonstration and feasibility study of this method. One of the main aims of this study is to demonstrate the applicability of the proposed concept in PCBAs, where the primary concerns are the low-cost manufacturability and available space. The other goal is to create an adaptation of the standard thermal characterization methodologies to deal with the specific dissipating components in the PCBA demonstrators. In the first part, the manufacturing technology is elaborated on, and its efficiency is characterized by thermal transient testing and Computational Fluid Dynamics (CFD) simulations. For these use cases, it was noted that the cumulative thermal resistance decreased by approximately 60% when a volumetric flow rate of 100 ccm was applied in the minichannels. In the second part, a more sophisticated technology demonstration is realized and characterized by adding the proposed embedded minichannel heat sink to an existing high-speed PCBA. A specific thermal transient testing was implemented specifically for this use case, and it was carried out on programmable logic devices by utilizing general-purpose programmable logic to construct the necessary measurement methods. In the future, this feature can be used in different logic circuit designs where it is not possible to determine the junction temperature directly.

Research and Design of Data Encryption Circuit based on D Flip-Flop

Since information technology is developing so quickly, the problem of data security has become increasingly prominent. Data encryption technology, as an important means of securing data transmission, plays a vital role in resisting network attacks and protecting privacy. In this paper, a data encryption circuit based on D flip-flop is studied, aiming to improve the efficiency and security of data encryption. First, this paper introduces the basic principles of data encryption and analyzes the application of D flip-flop in encryption circuit. Subsequently, the design principle of Moore’s state machine is elaborated, and encryption circuit is designed with the use of the state graph and state table. Further, this paper demonstrates the logic circuit design process., including the derivation of D-flip-flop input Circuit construction and Boolean expressions. This research provides a hardware implementation design solution for the design of data encryption circuits, which is expected to play a role in improving encryption speed and enhancing security.

A Flexible Smart Healthcare Platform Conjugated with Artificial Epidermis Assembled by Three-Dimensionally Conductive MOF Network for Gas and Pressure Sensing

The rising flexible and intelligent electronics greatly facilitate the noninvasive and timely tracking of physiological information in telemedicine healthcare. Meticulously building bionic-sensitive moieties is vital for designing efficient electronic skin with advanced cognitive functionalities to pluralistically capture external stimuli. However, realistic mimesis, both in the skin’s three-dimensional interlocked hierarchical structures and synchronous encoding multistimuli information capacities, remains a challenging yet vital need for simplifying the design of flexible logic circuits. Herein, we construct an artificial epidermal device by in situ growing Cu3(HHTP)2 particles onto the hollow spherical Ti3C2Tx surface, aiming to concurrently emulate the spinous and granular layers of the skin’s epidermis. The bionic Ti3C2Tx@Cu3(HHTP)2 exhibits independent NO2 and pressure response, as well as novel functionalities such as acoustic signature perception and Morse code-encrypted message communication. Ultimately, a wearable alarming system with a mobile application terminal is self-developed by integrating the bimodular senor into flexible printed circuits. This system can assess risk factors related with asthmatic, such as stimulation of external NO2 gas, abnormal expiratory behavior and exertion degrees of fingers, achieving a recognition accuracy of 97.6% as assisted by a machine learning algorithm. Our work provides a feasible routine to develop intelligent multifunctional healthcare equipment for burgeoning transformative telemedicine diagnosis.

Piezo-VFETs: Vacuum Field Emission Transistors Controlled by Piezoelectric MEMS Sensors as an Artificial Mechanoreceptor with High Sensitivity and Low Power Consumption.

As one of the most promising electronic devices in the post-Moore era, nanoscale vacuum field emission transistors (VFETs) have garnered significant attention due to their unique electron transport mechanism featuring ballistic transport within vacuum channels. Existing research on these nanoscale vacuum channel devices has primarily focused on structural design for logic circuits. Studies exploring their application potential in other vital fields, such as sensors based on VFET, are more limited. In this study, for the first time, the design of a vacuum field emission transistor (VFET) coupled with a piezoelectric microelectromechanical (MEMS) sensing unit is proposed as the artificial mechanoreceptor for sensing purposes. With a negative threshold voltage similar to an N-channel depletion-mode metal oxide silicon field effect transistor, the proposed VFET has its continuous current tuned by the piezoelectric potential generated by the sensing unit, amplifying the magnitude of signals resulting from electromechanical coupling. Simulations have been conducted to validate the feasibility of such a configuration. As indictable from the simulation results, the proposed piezoelectric VFET exhibits high sensitivity and an electrically adjustable measurement range. Compared to the traditional combination of piezoelectric MEMS sensors and solid-state field effect transistors (FETs), the piezoelectric VFET design has a significantly reduced power consumption thanks to its continuous current that is orders of magnitude smaller. These findings reveal the immense potential of piezoelectric VFET in sensing applications, building up the basis for using VFETs for simple, effective, and low-power pre-amplification of piezoelectric MEMS sensors and broadening the application scope of VFET in general.

Energy Aware Technology Mapping of Genetic Logic Circuits.

Energy and its dissipation are fundamental to all living systems, including cells. Insufficient abundance of energy carriers─as caused by the additional burden of artificial genetic circuits─shifts a cell's priority to survival, also impairing the functionality of the genetic circuit. Moreover, recent works have shown the importance of energy expenditure in information transmission. Despite living organisms being non-equilibrium systems, non-equilibrium models capable of accounting for energy dissipation and non-equilibrium response curves are not yet employed in genetic design automation (GDA) software. To this end, we introduce Energy Aware Technology Mapping, the automated design of genetic logic circuits with respect to energy efficiency and functionality. The basis for this is an energy aware non-equilibrium steady state model of gene expression, capturing characteristics like energy dissipation─which we link to the entropy production rate─and transcriptional bursting, relevant to eukaryotes as well as prokaryotes. Our evaluation shows that a genetic logic circuit's functional performance and energy efficiency are disjoint optimization goals. For our benchmark, energy efficiency improves by 37.2% on average when comparing to functionally optimized variants. We discover a linear increase in energy expenditure and overall protein expression with the circuit size, where Energy Aware Technology Mapping allows for designing genetic logic circuits with the energetic costs of circuits that are one to two gates smaller. Structural variants improve this further, while results show the Pareto dominance among structures of a single Boolean function. By incorporating energy demand into the design, Energy Aware Technology Mapping enables energy efficiency by design. This extends current GDA tools and complements approaches coping with burden in vivo.

Energy Aware Technology Mapping of Genetic Logic Circuits.

Energy and its dissipation are fundamental to all living systems, including cells. Insufficient abundance of energy carriers -as caused by the additional burden of artificial genetic circuits- shifts a cell's priority to survival, also impairing the functionality of the genetic circuit. Moreover, recent works have shown the importance of energy expenditure in information transmission. Despite living organisms being non-equilibrium systems, non-equilibrium models capable of accounting for energy dissipation and non-equilibrium response curves are not yet employed in genetic design automation (GDA) software. To this end, we introduce Energy Aware Technology Mapping, the automated design of genetic logic circuits with respect to energy efficiency and functionality. The basis for this is an energy aware non-equilibrium steady state (NESS) model of gene expression, capturing characteristics like energy dissipation -which we link to the entropy production rate- and transcriptional bursting, relevant to eukaryotes as well as prokaryotes. Our evaluation shows that a genetic logic circuit's functional performance and energy efficiency are disjoint optimization goals. For our benchmark, energy efficiency improves by 37.2% on average when comparing to functionally optimized variants. We discover a linear increase in energy expenditure and overall protein expression with the circuit size, where Energy Aware Technology Mapping allows for designing genetic logic circuits with the energy efficiency of circuits that are one to two gates smaller. Structural variants improve this further, while results show the Pareto dominance among structures of a single Boolean function. By incorporating energy demand into the design, Energy Aware Technology Mapping enables energy efficiency by design. This extends current GDA tools and complements approaches coping with burden in vivo.

Controllable electrical contact characteristics of graphene/Ga2X3 (X = S, Se) ferroelectric heterojunctions

Reducing the interface barrier between metals and semiconductors is crucial for designing high-performance optoelectronic devices based on van der Waals heterojunctions (HJs). This study proposes four models of HJs composed of graphene (GR) and Ga2X3 (X = S, Se) and systematically investigates their interface electronic properties, along with strain engineering and electric field effects. The results indicated that exploiting the interface dipole-induced potential step allows modulation of the Schottky barrier height (SBH) and contact type of the HJs by altering the contact interfaces. In the BGR/Ga2S3 HJs (BGR means GR positioned at the bottom of Ga2X3), only a small positive (negative) electric field is required to realize the transition from n-type Schottky to p-type Schottky (Ohmic) contacts. Also, strain engineering provides additional means for flexible and controllable contact types, facilitating the design of reversible logic circuits. It indicates the physical insights and strategic interventions of GR/Ga2X3 HJs tunable SBH and offers theoretical guidance for the design of two-dimensional ferroelectric nanodevices with high-quality electrical contact interfaces.

Implementation of first order statistical processor on FPGA for feature extraction

Statistical calculations on signals commonly used in feature extraction. In software processing, statistical computation is an easy task. However, providing a computer requires high costs for simple statistical processing. Another consideration is the need for implementation with real-time and portable processing. Therefore, an alternative device is needed, one of which is the field programmable gate array (FPGA). FPGA is a logic circuit board that can be reconfigured according to computing needs. FPGA can also be used as a prototyping of electronic chips. However, implementing statistical formulas in FPGA is interesting in developing its architecture. Therefore, this research proposes a logic circuit design that can be used for first-order statistical calculations. Statistical parameters include the mean, variance, standard deviation, skewness, and kurtosis. The validation test was performed on the electrocardiogram (ECG) signal series and compared with manual calculations. Validation shows that the mean and variance has very high accuracy with an average error of less than 0.06%.

Boosting Bidirectional Photoresponse with Wavelength Selectivity through Ambipolar Transport Modulation

AbstractNegative photoconductive phototransistors, referring to transistors that exhibit a decrease in photocurrent under illumination, have the potential to revolutionize optoelectronic applications involving light, such as optoelectronic logic circuits and visual neural simulation. Currently, achieving negative photoconductivity (NPC) requires complex material design or interface structure construction. However, achieving precise control over NPC behaviors poses a significant challenge. Herein, a simple yet effective strategy is demonstrated for realizing controllable NPC responses in organic phototransistors through ambipolar transport modulation. Due to the controversy between the preferred exciton dissociation/charge separation direction and the gate electric field driven charge drift direction, the main semiconductor channel (n‐ or p‐channel) exhibits NPC behavior under illumination. The validity of this mechanism has been confirmed through intensive studies by varying the component and combination of the p‐n heterostructure. Moreover, devices utilizing ambipolar transport exhibit a wavelength‐selectivity NPC response due to the absorption characteristics of the combined semiconductor materials. Most encouragingly, by incorporating both negative and positve photoconductivity along with wavelength‐selective responses, high‐contrast image sensing, information encryption and decryption, as well as optoelectronic logic circuit design is successfully achieved. This work promotes the design and development of bidirectional optoelectronic devices and offers a new route for developing attractive multifunctional optoelectronic devices.

Optimizing fault tolerance of RAM cell through MUX based modeling and design using symmetries of QCA cells

Extensive research is now being conducted on the design and construction of logic circuits utilizing quantum-dot cellular automata (QCA) technology. This area of study is of great interest due to the inherent advantages it offers, such as its compact size, high speed, low power dissipation, and enhanced switching frequency in the nanoscale domain. This work presents a design of a highly efficient RAM cell in QCA, utilizing a combination of a 3-input and 5-input Majority Voter (MV) gate, together with a 2 × 1 Multiplexer (MUX). The proposed design is also investigated for various faults such as single cell deletion, single cell addition and single cell displacement or misalignment defects. The circuit under consideration has a high degree of fault tolerance. The functionality of the suggested design is showcased and verified through the utilization of the QCADesigner tool. Based on the observed performance correlation, it is evident that the proposed design demonstrates effectiveness in terms of cell count, area, and latency. Furthermore, it achieves a notable improvement of up to 76.72% compared to the present configuration in terms of quantum cost. The analysis of energy dissipation, conducted using the QCAPro tool, is also shown for various scenarios. It is seen that this design exhibits the lowest energy dispersion, hence enabling the development of ultra-low power designs for diverse microprocessors and microcontrollers.

Design and analysis of logic circuits based on 8 nm double gate MOSFET

Design and analysis of logic circuits based on 8 nm double gate MOSFET

Biomaterial/Organic Heterojunction Based Memristor for Logic Gate Circuit Design, Data Encryption, and Image Reconstruction

AbstractBenefiting from powerful logic‐computing, higher packaging density, and extremely low electricity consumption, memristors are regarded as the most promising next‐generation of electric devices and are capable of realizing brain‐like neuromorphic computation. However, the design of emerging circuit devices based on memristors and their potential application in unconventional fields are very meaningful for achieving some tasks that traditional electronic devices cannot accomplish. Herein, a Cu/PEDOT:PSS‐PP:PVDF/Ti structured memristor is fabricated by using the polyvinylidene difluoride (PVDF) dopped biomaterial papaya peel (PP) and organic poly(3,4‐ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS) heterojunction as functional layer, which can be switched among resistive switching, self‐rectification effect, and capacitive behavior by adjusting the voltage bias/scan rate. Through further fitting of the data and simulating interfacial group reactions, this work innovatively proposes a charge conduction mode of device driven by Fowler–Nordheim tunneling, complexation reactions, and PEDOT:PSS pore removal. Finally, the regular logic gate and adder circuits are constructed based on the fabricated memristor, while a fully adder‐based encryption unit is designed to realize data encryption and image reconstruction. This work renders memristor compatible with logic circuits, widening a path toward data encryption and information security.

Teaching Design and Practice of "Three-wide Education" Integrating into Combinational Logic Circuit Design

This article explores the integration of "Three-Wide Education" into the course ‘Digital Electronic Technology’ with a specific focus on the content related to the design of combined logic circuits. As education continues to evolve, the goals of higher education have shifted from simply imparting knowledge to nurturing students' holistic development and actively engaging them in societal progress. In today's social context, the cultivation of high-caliber electronic information professionals with a strong sense of social responsibility has become a central objective of higher education. Consequently, curriculum-based "Three-Wide Education" has gained prominence as a pivotal component of higher education reform. Drawing upon the thematic elements of "Three-Wide Education" within the chapter on combinatorial logic circuit design, this article embarks on instructional design. The primary objective is to seamlessly integrate knowledge dissemination with value-based guidance through practical exercises in "Three-Wide Education" within the curriculum.

Design of memristor-based combinational logic circuits

Design of memristor-based combinational logic circuits

Design and analysis of fault-tolerant sequential logic circuits for safety-critical applications

Safety-critical systems used in applications that demand high levels of dependability, efficiency, and fault-tolerance often use sequential logic circuits in its design and implementation. The safety-critical digital system typically uses latches, flip-flops, and other memory elements, which are prone to the effects of natural faults and single event upsets (SEUs) caused by radiation-induced effects. The faults can lead to subsystem failures due to the continuous advancement in the realization of the small size transistor. To design a reliable digital-based system, it is essential to develop new fault-tolerance approaches that are integrated into the design of sequential logic circuits. This work proposes a novel fault-tolerant approach based on the redundancy of sequential logic circuit, which consists of a variety of design components, D flip-flop storage elements linked to a fault injection unit, a duplicate modular redundancy, and data monitoring units with a switching circuit. The experimental simulation results using a five-state Markov chain analysis model prove that the proposed fault-tolerant system can achieve 0.99999998 for reliability of the fault detection coverage (C) which equal to 0.99999. Finally, we believe that using this new approach of fault-tolerance and redundancy would improve the dependability and reliability of next generation safety-critical applications.

Multicolor Fluorescent Inks Based on Lanthanide Hybrid Organogels for Anticounterfeiting and Logic Circuit Design.

With the rapid development of information technology, the encrypted storage of information is becoming increasingly important for human life. The luminescent materials with a color-changed response under physical or chemical stimuli are crucial for information coding and anticounterfeiting. However, traditional fluorescent materials usually face problems such as a lack of tunable fluorescence, insufficient surface-adaptive adhesion, and strict synthesis conditions, hindering their practical applications. Herein, a series of luminescent lanthanide hybrid organogels (Ln-MOGs) were rapidly synthesized using a simple method at room temperature through the coordination between lanthanide ions and 2,6-pyridinedicarboxylic acid and 5-aminoisophthalic acid. And the multicolor fluorescent inks were also prepared based on the Ln-MOG and hyaluronic acid, with the advantages of being easy to write, color-adjustable, and water-responsive discoloration, which has been applied to paper-based anticounterfeiting technology. Inspired by the responsiveness of the fluorescent inks to water, we designed a logic system that can realize single-input logic operations (NOT and PASS1) and double-input logic operations (NAND, AND, OR, NOR, XOR). The encryption of a binary code can be actualized utilizing different luminescent response modes based on the logic circuit system. By adjusting the energy sensitization and luminescence mechanism of lanthanide ions in the gel structure, the information reading and writing ability of the fluorescent inks were verified, which has great potential in the field of multicolor pattern anticounterfeiting and information encryption.

Optimized design and investigation of novel reversible toffoli and peres gates using QCA techniques

The QCA is a revolutionary dominating transistor-less computational nanotechnology based on quantum dots. As such, it might be used in the next generation of quantum computational nano-electronics devices. New molecular materials like QCA are being developed for use in nanoscale devices and cables. The major objective of this research is to optimize the design and investigate numerous properties of a QCA reversible logic circuit design. These locations include, limited Toffoli Gate (TG) and Peres Gate (PG). To address the key problems associated with the physical integration of digital circuits is power consumption and power dissipation which leads to synchronization issues, this research proposes a novel reversible logic gates (RLG-TG) a single layer coplanar approach. RLG designs with minimal design area, latency, and quantum cell count (QCA) are given and implemented using a Bijection functional method. Using the QD-E (Energy) tool, the first-order energy dissipation of the proposed shape and the impact of output bias cell temperature are also investigated. The proposed circuit designs were tested using the CVSE parameters, which had high clock signal saturation energies of 9.8e-22 d (Jules), recovery times for damping factors of 1e-15 s, and relative dielectric constants of 12.90 for GaAs and AlGaAs. The number of quantum cells used by the described new RLG-TG and RLG-PG designs is decreased by 38.23 % and 21.14 %, respectively, when compared to the optimal RLG designs employed in the state-of-the-art RLG designs. In this investigation of the proposed four-bit EPG and OPG circuits occupies 18.91 % and 38.27 % less design area, requires 46.15 % and 46.25 % less number of cells, and both designs has been 66.66 % improvement in delay.

Droplet-based logic gates simulation of viscoelastic fluids under electric field

Nano and microfluidic technologies have shown great promise in the development of controlled drug delivery systems and the creation of microfluidic devices with logic-like functionalities. Here, we focused on investigating a droplet-based logic gate that can be used for automating medical diagnostic assays. This logic gate uses viscoelastic fluids, which are particularly relevant since bio-fluids exhibit viscoelastic properties. The operation of the logic gate is determined by evaluating various parameters, including the Weissenberg number, the Capillary number, and geometric factors. To effectively classify the logic gates operational conditions, we employed a deep learning classification to develop a reduced-order model. This approach accelerates the prediction of operating conditions, eliminating the need for complex simulations. Moreover, the deep learning model allows for the combination of different AND/OR branches, further enhancing the versatility of the logic gate. We also found that non-operating regions, where the logic gate does not function properly, can be transformed into operational regions by applying an external force. By utilizing an electrical induction technique, we demonstrated that the application of an electric field can repel or attract droplets, thereby improving the performance of the logic gate. Overall, our research shows the potential of the droplet-based logic gates in the field of medical diagnostics. The integration of deep learning classification algorithms enables rapid evaluation of operational conditions and facilitates the design of complex logic circuits. Additionally, the introduction of external forces and electrical induction techniques opens up new possibilities for enhancing the functionality and reliability of these logic gates.

Quantum analysis of a Mach–Zehnder interferometer with propagating a single photon Gaussian wave packet

In this paper, a Mach–Zehnder interferometer is analyzed with a single photon Gaussian wave packet at one of its input ports and vacuum state at the other input port. Various noises arising in the Mach–Zehnder interferometer such as photon flux noise and quadrature noise are mathematically analyzed. The effect of variation in device parameters on the power spectral density at the output ports of the Mach–Zehnder interferometer is studied. It is observed that the power spectral density of photon flux noise autocorrelation at the output ports of a Mach–Zehnder interferometer is a function of phase shift, whereas the power spectral density of quadrature noise autocorrelation at the output ports of a Mach–Zehnder interferometer is a function of frequency of a single photon wave packet and the phase shift. The analysis carried out in this paper will be helpful in understanding the quantum fluctuations in the design of quantum logic devices and circuits where the Mach–Zehnder interferometer is a core building block.