Design Of LC Voltage Controlled Oscillator Research Articles

Wide-tunable LC-VCO design with a novel active inductor

This paper presents the design of a wide-tunable, low-voltage, small-area LC voltage-controlled oscillator (LC-VCO). Instead of a spiral inductor, a novel active inductor is used in the conventional bottom-biased NMOS cross-coupled LC-VCO architecture. The oscillator, designed in TSMC 65 nm CMOS process and post-layout simulated in Cadence Design Suite, operates at a frequency range of 2.4 to 3.8 GHz and draws 8.5 mA from a 1.2 V supply. At a 1 MHz offset, the circuit has a phase noise of −80.22 dBc/Hz. The designed circuit has a differential output swing of 56.1 mV, and the percentage of total harmonic distortion (%THD) is determined as 3.47% in the nominal case. The designed LC-VCO consumes only 0.013 mm2 silicon area. Additionally, a buffer circuit is presented that can be utilized to make the oscillation rail-to-rail.

Power Efficient Implementation of Low Noise CMOS LC VCO using 32nm Technology for RF Applications

Voltage Controlled Oscillator (VCO) is an integral component of most of the receivers such as GSM, GPS etc. As name indicates, oscillation is controlled by varying the voltage at the capacitor of LC tank. By varying the voltage, VCO can generate variable frequency of oscillation. Different VCO Parameters are contrasted on the basis of phase noise, tuning range, power consumption and FOM. Out of these phase noise is dependent on quality factor, power consumption, oscillation frequency and current. So, design of LC VCO at low power, low phase noise can be obtained with low bias current at low voltage. Nanosize transistors are also contributes towards low phase noise. This paper demonstrates the design of low phase noise LC VCO with 4.89 GHz tuning range from 7.33-11.22 GHz with center frequency at 7 GHz. The design uses 32nm technology with tuning voltage of 0-1.2 V. A very effective Phase noise of -114 dBc / Hz is obtained with FOM of -181 dBc/Hz. The proposed work has been compared with five peer LC VCO designs working at higher feature sizes and outcome of this performance comparison dictates that the proposed work working at better 32 nm technology outperformed amongst others in terms of achieving low Tuning voltage and moderate FoM, overshadowed by a little expense of power dissipation.

A 2.4 GHZ Fully Integrated LC VCO Design Using 130 NM CMOS Technology

In this paper, a 2.4 GHz fully integrated LC voltage controlled oscillator (VCO) for RF wireless applications is presented. The VCO circuit is designed using TSMC 130 nm CMOS process. The circuit design is based on differential oscillator structure with cross-coupled NMOS transistors which achieves low power dissipation and low phase noise. Simulation and layout of the VCO is carried out using ADS Tool. The VCO operates from a supply voltage of 1.8 V and consumes 19.62 mW of power. After simulating the proposed design the VCO shows a phase noise of -128.68 dBc/Hz at 1 MHz offset frequency from a 2.4 GHz carrier signal. The frequency range of the VCO is from 2.36 GHz to 2.61 GHz when the control voltage changes from 0 to 2 V. The FOM is obtained as -183.73 dBc/Hz. The total chip area, including pads, occupies 0.7 mm × 0.7 mm.

Design of low power CMOS LC VCO for direct conversion transceiver

A low power 1.2 GHz LC differential voltage-controll ed oscillator (VCO) is designed for a direct conversion transceiver in 130 nm CMOS processes. It consists of a complementary current reuse structure and LC tank circuit. To produce a good tuning range and reduce losses in the tank circuit, modied inversion mode PMOS varactors and an on-chip inductor are designed with a better quality factor. The icker noise is reduced by the PMOS tail current source connected in parallel with the capacitance. The 1.2 GHz LC VCO achieves a phase noise value of {132 dBc/Hz at 1 MHz offset and the tuning range of the oscillator is from 1.128 to 1.27 GHz for the control voltage, tuning from 0 to 1.5 V. It dissipates 245 W power at 0.8 V supply voltage and thegure of merit is calculated as {199.7 dBc/Hz.

Design of Sub-1 mW CMOS LC VCO based on current reused topology with Q-enhancement and body-biased technique

A CMOS LC voltage controlled oscillator (VCO) based on current reused topology with low phase noise and low power consumption is presented for IEEE 802.11a (Seller et al. A 10GHz distributed voltage controlled oscillator for WLAN application in a VLSI 65nm CMOS process, in: IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 3–5 June, 2007, pp. 115–118.) application. The chip1 is designed with the tail current-shaping technique to obtain the phase noise −116.1dBc/Hz and power consumption 3.71mW at the operating frequency 5.2GHz under supply voltage 1.4V. The second chip of proposed VCO can achieve power consumption Sub 1mW and is still able to maintain good phase noise. The current reused and body-biased architecture can reduce power consumption, and better phase noise performance is obtained through raising the Q value. The measurement result of the VCO oscillation frequency range is from 5.082GHz to 5.958GHz with tuning range of 15.8%. The measured phase noise is −115.88dBc/Hz at 1MHz offset at the operation frequency of 5.815GHz. and the dc core current consumption is 0.71mA at a supply voltage of 1.4V. Its figure of merit (FOM) is −191dBc/Hz. Two circuits were taped out by TSMC 0.18μm 1P6M process.

An efficient PSP-based model for optimized cross-coupled MOSFETs in voltage controlled oscillator

This paper proposes an efficient PSP-based model for cross-coupled metal-oxide-semiconductor field-effect transistors (MOSFETs) with optimized layout in the voltage controlled oscillator (VCO). The model employs a PSP charge model to characterize the bias-dependent extrinsic capacitance instead of numerical functions with strong non-linearity. The simulation convergence is greatly improved by this method. An original scheme is developed to extract the parameters of the PSP charge model based on S-parameters measurement. The interconnection parasitics of the cross-coupled MOSFETs are modeled based on vector fitting. The model is verified with an LC VCO design, and exhibits excellent convergence during simulation. The results show improvements as high as 60.5% and 61.8% in simulation efficiency and accuracy, respectively, indicating that the proposed model better characterizes optimized cross-coupled MOSFETs in advanced radio frequency (RF) circuit design.

저전압용 전압제어발진기의 설계

본 논문에서는 WCDMA(Wide Code Division Multiple Access) 시스템 사양을 만족시키는 주파수 합성기 블록 중 위상잡음 및 전력소모의 최적 설계가 필요한 저전압 LC-VCO (voltage controlled oscillator)의 설계를 제안 하였다. 최적 설계를 위해 LC-tank의 손실성분을 보상하는 MOS트랜지스터의 전달컨덕턴스와 인덕턴스 평면에 여유이득 라인과 튜닝 범위 라인을 그어 설계 가능한 영역 내에서 위상잡음이 최소가 되는 파라미터 값을 구하였다. 모의실험 결과 위상잡음 특성은 1MHz옵셋에서 -113dBc/Hz였다. 최적 설계된 LC-VCO는 0.25um CMOS 공정을 이용하여 제작되었다. 칩 측정결과 LC-VCO의 위상잡음 특성은 1MHz 옵셋에서 -116dBc/Hz였다. 전력소모는 15mW였으며, Kvco는 370MHz/V였다. The design of low voltage LC-VCO(LC Voltage Controlled Oscillator) has been presented to optimize the phase noise and power consumption for the block of frequency synthesis to satisfy WCDMA system specification in this paper. The parameters for minimum phase noise has been obtained in the region of design, using the lines of the tuning range and the excess gain in the plane of the inductance and the transconductance of MOS transistor to compensate the loss of LC-tank. As a result of simulation, the phase noise characteristics is -113dBc/Hz for offset of 1MHz. The optimum designed LC-VCO has been fabricated using the process of 0.25um CMOS. As a result of measurement for fabricated chip, the phase noise characteristics is -116dBc/Hz for offset of 1MHz. The power consumption is 15mW, and Kvco is 370MHz/V.

CMOS LC voltage controlled oscillator design using multiwalled and single-walled carbon nanotube wire inductors

We have utilized our Multiwalled Carbon NanoTube (MWCNT) and Single-Walled Carbon NanoTube (SWCNT) bundle interconnects model in a widely used π model to study the performances of MWCNT and SWCNT bundle wire inductors and compared these with copper (Cu) inductors. The calculation results show that the Q-factors of Carbon NanoTube (CNT) wire (SWCNT bundle and MWCNT) inductors are higher than that of the Cu wire inductor. This is mainly due to much lower resistance of CNT and negligible skin effect in carbon nanotubes at higher frequencies. The application of CNT wire inductor in LC VCO is also studied and the Cadence/Spectre simulations show that VCOs with CNT bundle wire inductors have significantly improved performance such as the higher oscillation frequency and lower phase noise due to their smaller resistances and higher Q-factors. It is also noticed that CMOS LC VCO using a SWCNT bundle wire inductor has better performance when compared with the performance of LC VCO using the MWCNT wire inductor due to its lower resistance and higher Q-factor.