Design of Sub-1 mW CMOS LC VCO based on current reused topology with Q-enhancement and body-biased technique

Abstract

A CMOS LC voltage controlled oscillator (VCO) based on current reused topology with low phase noise and low power consumption is presented for IEEE 802.11a (Seller et al. A 10GHz distributed voltage controlled oscillator for WLAN application in a VLSI 65nm CMOS process, in: IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 3–5 June, 2007, pp. 115–118.) application. The chip1 is designed with the tail current-shaping technique to obtain the phase noise −116.1dBc/Hz and power consumption 3.71mW at the operating frequency 5.2GHz under supply voltage 1.4V. The second chip of proposed VCO can achieve power consumption Sub 1mW and is still able to maintain good phase noise. The current reused and body-biased architecture can reduce power consumption, and better phase noise performance is obtained through raising the Q value. The measurement result of the VCO oscillation frequency range is from 5.082GHz to 5.958GHz with tuning range of 15.8%. The measured phase noise is −115.88dBc/Hz at 1MHz offset at the operation frequency of 5.815GHz. and the dc core current consumption is 0.71mA at a supply voltage of 1.4V. Its figure of merit (FOM) is −191dBc/Hz. Two circuits were taped out by TSMC 0.18μm 1P6M process.