Interface Circuit Design Research Articles

Design and Implementation of Interface Circuits Intended for Printed Piezoelectric Micropower Harvesters on Flexible Substrates

Interface circuits with low power dissipation is proposed and implemented, which is useful for efficient AC/DC voltage conversion of thin-film piezoelectric micro-power stack mounted harvesters. The focus is on low-power (< 1 μW) elements consisting of printed PVDF-TrFE piezoelectric polymer on BaSrTiO3 coated flexible substrate with total thickness of the stack 3.1 μm. Using silver thin films as bottom and top electrodes, the samples exhibited stable piezoelectric rms voltage between 200 mV and 400 mV produced from functional area of ∼1.5 cm2 when stimulates it with sine-wave vibration with frequency of 50 Hz and intensity equivalent to mass loading between 1–80 g. The current registered from a single harvesting element is not greater than 1 μA. For this type of harvesters two power processing circuits intended are designed and built. The first circuit is a voltage doubler, for which the rectified output voltage is approximately equal to twice of the amplitude of the input voltage. The second circuit is a voltage quadrupler; as compared to the first one it provides higher voltage for charging a small and thin-size chip supercapacitor connected to the output port, but due to diodes voltage drops a smaller value of the energy efficiency can be obtained. For the implementation of the electronic circuits, low-power Schottky diodes with a forward voltage below 100 mV at current up to 0.1 mA are chosen. An experimental study to verify the efficiency of the proposed circuits is performed with laboratory made thin-film piezoelectric harvesters.

Design and Analysis of a Relaxation Oscillator-Based Interface Circuit for LVDT

This paper presents a simple, novel interfacing scheme for linear variable differential transformer (LVDT) that does not require a precise sine wave oscillator (with stable amplitude and frequency) for excitation or any phase matching circuit like traditional methods. The primary and the secondary coils of the LVDT are integral parts of a relaxation oscillator (RO). The RO injects a current waveform with a triangular shape through the primary coil which in turn induces a square-shaped voltage waveform in the secondary coils. The RO utilizes the amplitudes of those waveforms and generates a pulsewidth modulation (PWM) output signal whose duty cycle ratio is proportional to the measurand, core position. This quasi-digital PWM signal is passed through a low-pass filter to obtain an analog output. PWM time period measurement using a counter yields a digital output. This method guarantees good stability since the output is dependent only on a pair of dc reference voltages apart from the transformation constant of the sensor. A detailed analysis of the sources of error, their effect on the performance of the scheme and appropriate design choices for error mitigation are also presented. A prototype of the proposed circuit was built and tested in the laboratory. The nonlinearity error noted from the tests conducted was less than 0.16% for the analog output and 0.18% for the digital output. A resolution of up to 11 bits was achieved for the digital output.

Design of SECE Energy Harvest Interface Circuit with High Voltage Comparator for Smart Sensor

Design of SECE Energy Harvest Interface Circuit with High Voltage Comparator for Smart Sensor

A 9.1ENOB 200MS/s Asynchronous SAR ADC With Hybrid Single-Ended/Differential DAC in 55-nm CMOS for Image Sensing Signals

A 9.1ENOB 200 MS/s asynchronous SAR analog-to-digital converter (ADC) dealing with image sensing signals is presented in this paper. The proposed ADC, designed in 55-nm CMOS process technology, can work in both single-ended and differential modes. To guarantee the ADC linearity, a symmetrical switching method is adopted. To ensure the reference accuracy when the ADC is in operation, a 1.2-V on-chip quick-response LDO, which works under a 2.5-V supply, is also integrated. To overcome the need for a clock-generation circuit and avoid a high-speed interface circuit design, asynchronous clock logic is chosen. In addition, the comparison cycle is adjusted dynamically to guarantee the DAC settling and improve the ADC throughput. In the differential operation mode, the proposed SAR ADC exhibits a peak signal-to-noise-and-distortion ratio (SNDR) of 56.5 dB and a peak spurious-free-dynamic-range (SFDR) of 68 dB with the Nyquist input, at a 200-MS/s output rate. The ADC consumes 2.74 mW, resulting in a figure-of-merit (FOM) of 25-fJ/conversion-step. Meanwhile, in the single-ended mode, the SNDR and SFDR of the ADC are 53and 64 dB, respectively. And the power consumption is 2.25 mW, resulting in an FOM of 31-fJ/conversion-step. The area of the proposed ADC is $280\times 380\,\,\mu \text{m}^{2}$ and the ADC core occupies an active area of only $140\times 250\,\,\mu \text{m}^{2}$ .

Electromagnetic Energy Harvester Interface Design for Wearable Applications

This brief presents an interface design for electromagnetic energy harvesting for wearable applications. A transducer design is proposed. Multiple segments of coils with alternating winding directions improve the induced voltage and power. Due to the source’s wideband nature in target applications, we avoid the use of springs common in conventional designs. The corresponding equivalent circuit model is presented. A system-level analysis is then performed that leads to the following power interface circuit design. It includes a differential rectifier and a switched-inductor boost converter. The harvested power is maximized with a constant-resistance load that can be adjusted through a variable-gain amplifier’s gain. Implemented in a ${0.18{-}\mu }\text{m}$ CMOS process and tested at 20 Hz, measurement results show >80% impedance matching efficiency with >0.7-V input voltages. The system is able to harvest ${\sim }320~{\mu }\text{W}$ when shaken by hand at 2.5~3 Hz.

Designand application of data aquistion interface circuit

A commitment to condition monitoring involves the operators of plant in the conduct of a range of activities. These activities may be complicated in nature and indeed may often be performed automatically under computer control. They can, however, always be down into a relatively small number of easily identifiable functional tasks. This makes it much easier to identify the common elements of machine condition monitoring schemes. A proposed interface circuit design and application will be further explain in this paper, the implemented monitoring unit circuit also illustrated, see appendix A. Two scenarios presented in this paper, first ten turns assume to be shorted, and in the second thirty turns shorted to show the difference in the amplitude of frequencies at each case. This paper present. An improvement in three-phase squirrel-cage induction motor stator inter-turn fault detection and diagnosis based on a neural network approach is presented.

Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

Abstract. Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI) substrate to form a Hybrid System-in-Foil (HySiF), which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing) of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA) in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC). The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC), a differential difference amplifier (DDA), and a 10-bit successive approximation register (SAR) ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

A low noise interface circuit design of micro-machined gyroscope**Project supported by the National Natural Science Foundation of China (No. 61204121), the National Hi-Tech Research and Development Program of China (No. 2013AA041107), and the Fundamental Research Funds for the Central Universities (No. HIT.NSRIF.2013040).

The analyses of MEMS gyroscope interface circuit on thermal noise, 1/f noise and phase noise are made in this paper. A closed-loop differential driving circuit and a low-noise differential detecting circuit based on the high frequency modulation are designed to limit the noise. The interface chip is implemented in a standard 0.5 μm CMOS process. The test results show that the resolution of sensitive capacity can reach to 6.47 × 10−20 F at the bandwidth of 60 Hz. The measuring range is ± 200°/s and the nonlinearity is 310 ppm. The output noise density is . The angular random walk (allen-variance) is and the bias instability is 2.63°/h.

Design of a high precision digital interface circuit for capacitive MEMS accelerometers with floating point ADC

Traditional analog blocks such as integrators are widely used in high precision MEMS accelerometers. However there is few cost-effective method to address the problem of analog integrators’ output saturation due to the integrators’ input offsets. A high precision digital capacitive MEMS accelerometer interface based on the traditional capacitive MEMS accelerometer sigma-delta interface is proposed to address this issue. An instantaneous floating point analog-to-digital converter (IFP ADC) is proposed to convert the analog frond-end amplifier (AFE) output signal to digital signal. The IFP ADC is very effective to digitalize the signal of the proposed interface circuit output, which is similar to Gaussian distribution. A Matlab simulation model is developed to evaluate the theory model. The implementation of digital loop filter realized in a FPGA board can overcome integrator offset issue. In addition, it is much easier to optimize a digital loop filter's parameter and reduce the chip cost. In this work, the AFE and voltage reference etc. are successfully fabricated by using the 0.18µm mixed-signal CMOS process. The sensitivity and the noise floor of the AFE are respectively 0.71V/pF and 3.16µV/rt(Hz) in an open loop measurement. The evaluation PCB experimental result shows that the noise floor of the system is −135dBg/rt(Hz).

Low power electronic interface for electrostatic energy harvesters

This paper presents design and simulation of a power electronic interface circuit for MEMS electrostatic energy harvesters. The designed circuit is applicable to highly miniaturized electrostatic harvesters with small transducer capacitances below 10 pF. It is based on comb- drive harvesters with two anti-phase capacitors that are connected as charge pumps and uses a flyback-path scheme. Controlled activation and deactivation of sub-circuits, some by help of clocking, were exploited to reduce power consumption down to 1.03 μW. Net power generation can be achieved with as low initial voltage as 3.0 V.

A fully autonomous power management interface for frequency up-converting harvesters using load decoupling and inductor sharing

This paper presents the design and simulation results of a self-starting electrical interface circuit for Parametric Frequency Increased Generator (PFIG) vibrational energy harvesters. A significant challenge with these types of harvesters is the ring down of the transducer, introducing an exponential decrease in efficiency when interfaced with standard passive rectifiers. This work aims to address these challenges by interfacing a standard active rectifier to a buck-boost stage in order to decouple the load and always provide an optimal impedance to the transducer. Because PFIG harvesters have two outputs, an inductor sharing technique allows the hardware to be reused. The active buck-boost power management circuit is designed for XFAB's 0.35 μm 2P5M CMOS process. It can provide an efficiency between 75% - 93% for input voltages in the range of 0.5 - 2 V, reaching its maximum efficiency at 1.8 V. The active power consumption of the power converter is 800 nW. The system can start from as low as 800 mV of input voltage and 3 μW of input power.

A Smart Home Test Bed for Undergraduate Education to Bridge the Curriculum Gap From Traditional Power Systems to Modernized Smart Grids

There is a worldwide trend to modernize old power grid infrastructures to form future smart grids, which will achieve efficient, flexible energy consumption by using the latest technologies in communication, computing, and control. Smart grid initiatives are moving power systems curricula toward smart grids. Although the components of smart grids fall within the broader discipline of electrical and computer engineering, undergraduate students are rarely assigned single design projects that require classic power systems knowledge combined with communication, computing, and control. Therefore, as a significant step toward potential curriculum changes, this paper presents such a project, a smart home test bed based on the pedagogical model of project-based learning (PBL) for undergraduate education. The proposed test bed allows undergraduates to gain key knowledge in smart grid topics, such as flattening demand peaks, real-time price response, wireless sensor networks, machine learning, pattern recognition, embedded system programming, user interface design, circuit design, and databases. This is well aligned with smart grid initiatives and provides a platform for students to develop their creativity in engineering design. It also offers real-life examples to be used for raising general public awareness of energy conservation.

Design and Realization of Smart Home System Based on Wireless Sensor Networks

The paper takes STM32 microcontroller as the core. The UIP protocol stack is transplanted to STM32 to construct embedded web server and wireless sensor networks is used to construct the internal network of smart home. In combination with GSM communication technology, a smart home control system with the advantages of reliability, simplicity and flexibility is designed. In addition, this article also introduced a low power wireless receiving and transmitting chip CC 1100 in detail, completed software and hardware design of wireless receiving and transmitting module. Aspect of hardware design, completed the peripheral circuit design of CC 1100 and design of interface circuit .Aspect of software design, completed setting of register, communication of SPI with single chip and receiving and transmitting of data, has given the flow chart and the procedure.

Life Lessons: Zaghloul has worn many hats [Women to Watch

An electrical engineer by trade, Mona Zaghloul wears many hats and has an impressive resume including IEEE Fellow, professor, and director at George Washington University (GWU) and the National Science Foundation (NSF). Her work has spanned decades of projects in topics such as circuits and systems, microelectronics system design, very-large-scale integration circuit design, radio frequency microelectromechanical systems (RF-MEMS), neural networks, MEMS sensor systems, and biosensors and their interface circuit design. She views engineering as a rewarding career and hopes that many women will choose it.

Study on GPRS Mobile Terminal System for Rural Informatization

In this paper, GPRS module, including the design and implementation of the telephone terminal interface circuit design TV interface circuit, interface GPRS module and starting circuit are designed based on ARM embedded platform. Software is also designed primarily Bootloader and Linux kernel porting, system part of the driver, the results of the design through experimental verification, the results show that the system can communicate data, you can use AT commands to achieve messaging and voice capabilities.

Testable cross-power domain interface (CPDI) circuit design in monolithic 3D technology

Optimizing energy consumption for electronic systems has been an important design consideration. Multipower domain design is widely used for low-power and high-performance applications. Data transfer between power domains needs a cross-power domain interface (CPDI). The existing level-conversion flip-flop (LCFF) structures all need dual power rails, which lead to large area and performance overhead. In this article, we propose a scanable CPDI circuit, utilizing monolithic 3D technology. This interface functions as a flip-flop and provides reliable data conversion from one power domain to another. It has a built-in scan feature, which makes it a testable design. Our design separates power rails in each tier, substantially reducing physical design complexity and area penalty. The design is implemented in a 20nm, 28nm, and 45nm low-power technology. It shows a 20%--35% smaller insertion delay compared to normal designs. This proposed design also shows scalability and better energy consumption than previous LCFF circuits.

Research on Serial Communication in the Permanent Magnet Linear Synchronous Motor Vertical Transportation System

The serial communication design based on DSP in the permanent magnet linear synchronous motor vertical transportation system is presented in this paper. The control system structure and fundamental are introduced briefly at first. Then, the realization of serial communication between the TMS320VC5402 and PC by asynchronous serial communications chip TL16C550C is introduced in detail. Finally, the design of system hardware interface circuit and software programs are presented. The features of this system include simple programming , good reliability and real-time capability.

RFID-Based Card Reader Design

This paper designs an RFID-based reader of which functional module and hardware design are also comprehensively described. The interface circuit between MCU and MF RC500 which is also the invitation point effectively solves the difficulty in RF interface circuit design. The proposed reader is applied in the smart-card system of campus and property management system and has great performance.

基于DSP和S1D13305的EL屏显示控制系统设计

An environmental adaptability display control system was designed for the wild harsh environment.The system is based on the design of the EL screen controlled by DSP and S1D13305.Both the interface circuit and software design methods between DSP and display control chip were discussed.The problem that the internal character content of the display control chip is single was solved.The initialization procedures of the system settings and display control chip settings were provided.The display driving module was developed.After the actual assessment and application,the display system in the wild harsh environment is stable,and has better display quality in actual use. The display system can achieve the desired effect.

基于AM-OLED立体显示接口电路的设计

基于AM-OLED立体显示接口电路的设计