Design Of Interconnection Networks Research Articles

The design, analysis and simulation of a fault-tolerant interconnection network supporting the fetch-and-add primitive

The combining multistage interconnection network uses 4*4 switches as switching elements and introduces an extra stage of such switches and links to create four independent paths between any source-destination pair. Four copies of every message are sent through the network simultaneously. The scheduling discipline, the design of the switching elements to support the discipline, and the theoretical proof of correctness of the design constitute the key contributions of this study. Estimates are provided of various network parameters as a function of the workload, using analytical models and detailed network simulations. It is shown that the proposed design for fault tolerance is more cost-effective than the brute-force technique of having multiple copies of the network. >

Analysis and design of nonequivalent multistage interconnection networks

Nonequivalence of multistage interconnection networks is established by obtaining a reduced graph model and then partitioning it into several bipartite subgraphs. This is shown to transform nonequivalence to nonisomorphism, which can be easily determined by examining the intrinsic characteristics of undirected loops. A reverse process allows the design of nonequivalent networks.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Connectivity of Imase and Itoh digraphs

An important problem in the design of efficient interconnection networks consists of finding digraphs with a minimal diameter for a given number of nodes n and a given degree d. The best family known at present, denoted by G(n,d), has been proposed by Imase and Itoh, ibid., vol.C-32, p.782-4 (1983). Its vertex set is the set of integers modulo n and its arc set A is defined as A=((x,y)/y identical to -dx-a, 1 1, and d-1 otherwise. >

A Multiprocessor Architecture for the (M, L)-Algorithm Suitable for VLSI Implementation

The <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(M, L)</tex> -algorithm has been widely used in speech and image encoding. Recently, use of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(M, L)</tex> -Iike algorithms has been suggested for decoding phase codes. With its ever-increasing use, there arises a need to explore architectures suitable for real-time applications. Toward this end, we present a multiprocessor architecture for the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(M, L)</tex> algorithm that employs an SIMD (single instruction-multiple data) machine structure. The considerations involved in interconnection network design are discussed. The main functions of the network controller are switch state selection and synchronization. The number of switching elements required is significantly less than the elements required in the universal permutation network. These features make this architecture suitable for VLSI implementation. The tradeoff between number of processors and encoding time is also discussed.

Interconnection networks: Physical design andperformance analysis

This paper considers various physical constraints which influence the design of interconnection networks used in multiprocessor systems. Design expressions are presented for implementing an N log N packet passing interconnection network composed of circuit switched crossbar chip modules. Expressions reflecting chip level and board level pin and area constraints are derived and used to determine the network delay expected at a given clock frequency. Logic and memory delay, signal path delay, clock skew, and clock distribution delay parameters are defined and used to determine the maximum frequency which can be obtained with a given design. An example 2048 × 2048 network design is considered. This example indicates that using aggressive packaging and MOS technology, a clock frequency of about 40 Mhz is achievable. However, even at this frequency, this network would result in a one-way delay (ignoring blocking and hot spot delays) of about 1 μsec. A read operation from memory requiring a round trip would thus require about 2 μsec. This represents considerable slowdown when compared with accessing strictly local memory and appears to be a major problem in the design of network centered multiprocessor architectures.

A modified version of chordal ring

Topological design of interconnection network is a key factor of developing parallel/distributed processing systems composed of a large number of microcomputer modules. For this purpose a double-chordal ring interconnection network was proposed. The most attractive of its advantages is that for an optimally designed network withN modules its diameter can be reduced toO(N 1/3) compared withO(N 1/2) for a simple chordal ring. The essential properties of double-chordal ring network are presented, and formulae for calculating its diameter are derived. These formulae lead to a distributed computational routing algorithm and a way of optimization of the network parameters (maximal number of nedes and optimal chordal lengths) for a given diameter.

Some large graphs with given degree and diameter

AbstractThis paper considers the (Δ, D) problem: to maximize the order of graphs with given maximum degree Δ and diameter D, of importance for its implications in the design of interconnection networks. Two cubic graphs of diameters 5 and 8 and orders 70 and 286, respectively, and a graph of degree 5, diameter 3 and order 66 are presented, which improve the previously known orders for these values of Δ and D. By its construction, these graphs have a large automorphism group.

An Architectural Comparison of Dataflow Systems

A Distributed Computer System, or DCS, based on the dataflow model of computation has the potential to concurrently execute a large number of tasks employing potentially thousands of processors. Since control has to be distributed and asynchronous in such a DCS, several new challenges appear in the design of processors, momory, and interconnection networks. Some of the challenges in the design of processors is presented in this article. An architectural comparison of seven dataflow processors based on sixteen criteria forms the major part of the article.

Design and analysis of fault-tolerant multistage interconnection networks with low link complexity

Design and analysis of fault-tolerant multistage interconnection networks with low link complexity

Design of multistage interconnection networks

Interconnection networks have extensive applications in switching and reconfigurable multiprocessor systems. A number of multistage networks which can achieve a limited number of permutations have been discussed in the literature [1]. On the other hand, rearrangeable networks [6] have the property that any idle input/output pair can be connected. In most parallel-processing applications, a specified set of input/output connection patterns are required. Often these patterns cannot be achieved by networks like shuffle exchange, cube, Omega and baseline. The chief objective of the paper is to present a methodology for multistage interconnection network design. This design generally requires less switching elements than the rearrangeable network. The paper relies on the formulation of a transmittance matrix for the network. The properties of this matrix are studied with particular focus on rearrangeable networks. A control algorithm which determines the switch states required to achieve a particular permutation is established. The switching algebraic approach is particularly well suited to address the network design problem, because the switch states are explicitly exhibited in the transmittance matrix.