High-performance Microprocessor Design Research Articles

Efficient Aspect Verification and Debugging of High-Performance Microprocessor Designs

Efficient Aspect Verification and Debugging of High-Performance Microprocessor Designs

Kill the Program Counter

Data prefetching and cache replacement algorithms have been intensively studied in the design of high performance microprocessors. Typically, the data prefetcher operates in the private caches and does not interact with the replacement policy in the shared Last-Level Cache (LLC). Similarly, most replacement policies do not consider demand and prefetch requests as different types of requests. In particular, program counter (PC)-based replacement policies cannot learn from prefetch requests since the data prefetcher does not generate a PC value. PC-based policies can also be negatively affected by compiler optimizations. In this paper, we propose a holistic cache management technique called Kill-the-PC (KPC) that overcomes the weaknesses of traditional prefetching and replacement policy algorithms. KPC cache management has three novel contributions. First, a prefetcher which approximates the future use distance of prefetch requests based on its prediction confidence. Second, a simple replacement policy provides similar or better performance than current state-of-the-art PC-based prediction using global hysteresis. Third, KPC integrates prefetching and replacement policy into a whole system which is greater than the sum of its parts. Information from the prefetcher is used to improve the performance of the replacement policy and vice-versa. Finally, KPC removes the need to propagate the PC through entire on-chip cache hierarchy while providing a holistic cache management approach with better performance than state-of-the-art PC-, and non-PC-based schemes. Our evaluation shows that KPC provides 8% better performance than the best combination of existing prefetcher and replacement policy for multi-core workloads.

Kill the Program Counter

Data prefetching and cache replacement algorithms have been intensively studied in the design of high performance microprocessors. Typically, the data prefetcher operates in the private caches and does not interact with the replacement policy in the shared Last-Level Cache (LLC). Similarly, most replacement policies do not consider demand and prefetch requests as different types of requests. In particular, program counter (PC)-based replacement policies cannot learn from prefetch requests since the data prefetcher does not generate a PC value. PC-based policies can also be negatively affected by compiler optimizations. In this paper, we propose a holistic cache management technique called Kill-the-PC (KPC) that overcomes the weaknesses of traditional prefetching and replacement policy algorithms. KPC cache management has three novel contributions. First, a prefetcher which approximates the future use distance of prefetch requests based on its prediction confidence. Second, a simple replacement policy provides similar or better performance than current state-of-the-art PC-based prediction using global hysteresis. Third, KPC integrates prefetching and replacement policy into a whole system which is greater than the sum of its parts. Information from the prefetcher is used to improve the performance of the replacement policy and vice-versa. Finally, KPC removes the need to propagate the PC through entire on-chip cache hierarchy while providing a holistic cache management approach with better performance than state-of-the-art PC-, and non-PC-based schemes. Our evaluation shows that KPC provides 8% better performance than the best combination of existing prefetcher and replacement policy for multi-core workloads.

Challenges of cell selection algorithms in industrial high performance microprocessor designs

Timing-constrained power-driven gate sizing has aroused lot of research interest after the recent discrete gate sizing contests organized by International Symposium on Physical Design. Since then, there are plenty of research papers published and new algorithms are proposed based on the contest formulation. However, almost all (new and old) papers in the literature ignore the details of how power-driven gate sizing fits in industrial physical synthesis flows, which limits their practical usage. This paper aims at filling this knowledge gap. We explain our approach to integrate a state-of-the-art Lagrangian Relaxation-based gate sizing into our actual physical synthesis framework, and explain the challenges and issues we observed from the point of view of VLSI design flows.

Impact of Local Interconnects on Timing and Power in a High Performance Microprocessor

In nanometer technologies, local interconnects are believed to cause a major impact on timing and power in VLSI circuits. To assess the impact of the interconnects on timing and power in a real high performance microprocessor design in a quantitative manner, this article presents results from an extensive study carried out on RTL-to-layout synthesized blocks in a 45-nm technology core. The study shows that the interconnects in these blocks account for 30% of the cycle time, on an average, on the worst internal timing paths and contribute nearly one-third to the power dissipation. This points to severity of impact due to the interconnects in today's high performance designs.

Scan-Based Speed-Path Debug for a Microprocessor

Identifying the actual speed limiting paths in silicon using traditional functional microprocessor tests can be very time-consuming and expensive because of limited observability of internal signals. This paper presents the development of a promising scan-based speed path diagnosis methodology and illustrates its application to a high performance microprocessor design.

Postgrid Clock Routing for High Performance Microprocessor Designs

Designing a high-quality clock network is very important in very large-scale integrated designs today, as it is the clock network that synchronizes all the elements of a chip, and it is also a major source of power dissipation of a system. Early study by Pham in 2006 shows that about 18.1% of the total clock capacitance was due to this postgrid clock routing (i.e., lower mesh wires plus clock twig wires). In this paper, we proposed a partition-based path expansion algorithm to solve this postgrid clock routing problem effectively. Experimental results on industrial test cases show that our algorithm can improve over the latest work by Shelar on this problem significantly by reducing the wire capacitance by 24.6% and the wirelength by 23.6%.

General Parameterized Thermal Modeling for High-Performance Microprocessor Design

This paper proposes a new parameterized dynamic thermal modeling algorithm for emerging thermal-aware design and optimization for high-performance microprocessor design at architecture and package levels. Compared with existing behavioral thermal modeling algorithms, the proposed method can build the compact models from more general transient power and temperature waveforms used as training data. Such an approach can make the modeling process much easier and less restrictive than before and, thus, more amenable for practical measured data. The new method, called ParThermSID, consists of two steps. First, the response surface method based on second-order polynomials is applied to build the parameterized models at each time point for all of the given sampling nodes in the parameter space. Second, an improved subspace system identification method, called ThermSID, is employed to build the discrete state space models, by construction of the Hankel matrix and state space realization, for each time-varying coefficient of the polynomials generated in the first step. To overcome the overfitting problems of the subspace method, the new method employs an overfitting mitigation technique to improve model accuracy and predictive ability. Experimental results on a practical quad-core microprocessor show that the generated parameterized thermal model matches the given data very well. The compact models generated by ParThermSID also offer two orders of magnitude speedup over the commercial thermal analysis tool FloTHERM on the given example. The results also show that ThermSID is more accurate than the existing ThermPOF method.

Implementation of ALU Using Asynchronous Design

Power consumption has become one of the biggest challenges in design of high performance microprocessors. In this paper we present a design technique using GALs (Globally-Asynchronous Locally- Synchronous) for implementing asynchronous ALUs, which aims to eliminate the global clock. Here ALUs are designed with delay insensitive dual rail four phase logic and CMOS domino logic. It ensures economy in silicon area and potentially for low power consumption. This has been described and implemented in order to achieve a high performance in comparison with synchronous and available asynchronous design. Also simulation results, show significant reduction in the number of transistors as well as delay.

Architecting high-performance energy-efficient soft error resilient cache under 3D integration technology

Radiation-induced soft error has become an emerging reliability threat to high performance microprocessor design. As the size of on chip cache memory steadily increased for the past decades, resilient techniques against soft errors in cache are becoming increasingly important for processor reliability. However, conventional soft error resilient techniques have significantly increased the access latency and energy consumption in cache memory, thereby resulting in undesirable performance and energy efficiency degradation. The emerging 3D integration technology provides an attractive advantage, as the 3D microarchitecture exhibits heterogeneous soft error resilient characteristics due to the shielding effect of die stacking. Moreover, the 3D shielding effect can offer several inner dies that are inherently invulnerable to soft error, as they are implicitly protected by the outer dies. To exploit the invulnerability benefit, we propose a soft error resilient 3D cache architecture, in which data blocks on the soft error invulnerable dies have no protection against soft error, therefore, access to the data block on the soft error invulnerable die incurs a considerably reduced access latency and energy. Furthermore, we propose to maximize the access on the soft error invulnerable dies by dynamically moving data blocks among different dies, thereby achieving further performance and energy efficiency improvement. Simulation results show that the proposed 3D cache architecture can reduce the power consumption by up to 65% for the L1 instruction cache, 60% for the L1 data cache and 20% for the L2 cache, respectively. In general, the overall IPC performance can be improved by 5% on average.

Parameterized architecture-level dynamic thermal models for multicore microprocessors

In this article, we propose a new architecture-level parameterized dynamic thermal behavioral modeling algorithm for emerging thermal-related design and optimization problems for high-performance multicore microprocessor design. We propose a new approach, called ParThermPOF , to build the parameterized thermal performance models from the given accurate architecture thermal and power information. The new method can include a number of variable parameters such as the locations of thermal sensors in a heat sink, different components (heat sink, heat spreader, core, cache, etc.), thermal conductivity of heat sink materials, etc. The method consists of two steps: first, a response surface method based on low-order polynomials is applied to build the parameterized models at each time point for all the given sampling nodes in the parameter space. Second, an improved Generalized Pencil-Of-Function (GPOF) method is employed to build the transfer-function-based behavioral models for each time-varying coefficient of the polynomials generated in the first step. Experimental results on a practical quad-core microprocessor show that the generated parameterized thermal model matches the given data very well. The compact models by ParThermPOF offer two order of magnitudes speedup over the commercial thermal analysis tool FloTHERM on the given examples. ParThermPOF is very suitable for design space exploration and optimization where both time and system parameters need to be considered.

Architecture-Level Thermal Characterization for Multicore Microprocessors

This paper investigates a new architecture-level thermal characterization problem from a behavioral modeling perspective to address the emerging thermal related analysis and optimization problems for high-performance multicore microprocessor design. We propose a new approach, called <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ThermPOF</i> , to build the thermal behavioral models from the measured or simulated thermal and power information at the architecture level. <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ThermPOF</i> first builds the behavioral thermal model using the generalized pencil-of-function (GPOF) method. Owing to the unique characteristics of transient temperature changes at the chip level, we propose two new schemes to improve the GPOF. First, we apply a logarithmic-scale sampling scheme instead of the traditional linear sampling to better capture the temperature changing behaviors. Second, we modify the extracted thermal impulse response such that the extracted poles from GPOF are guaranteed to be stable without accuracy loss. To further reduce the model size, a Krylov subspace-based reduction method is performed to reduce the order of the models in the state-space form. Experimental results on a real quad-core microprocessor show that generated thermal behavioral models match the given temperature very well.

Design Migration From Peripheral ASIC Design to Area-I/O Flip-Chip Design by Chip I/O Planning and Legalization

Due to higher input/output (I/O) count and power delivery problem in deep submicrometer (DSM) regime, flip-chip technology, especially for area-array architecture, has provided more opportunities for adoption than traditional peripheral bonding design style in high-performance application-specific integrated circuit and microprocessor designs. However, it is hard to tell which technique can provide better design cost edge in usually concerned perspectives. In this paper, we present a methodology to convert a previous peripheral bonding design to an area-I/O flip-chip design. It is based on an I/O buffer modeling and an I/O planning algorithm to legalize I/O buffer blocks with core placement without sacrificing much of the previous optimization in the original core placement. The experimental results have shown that we have achieved better area and I/O wirelength in area-IO flip-chip configuration (especially for pad-limit designs), compared with peripheral bonding configuration in packaging consideration.

VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects

Within-die parameter variation poses a major challenge to high-performance microprocessor design, negatively impacting a processor's frequency and leakage power. Addressing this problem, this paper proposes a microarchitecture-aware model for process variation-including both random and systematic effects. The model is specified using a small number of highly intuitive parameters. Using the variation model, this paper also proposes a framework to model timing errors caused by parameter variation. The model yields the failure rate of microarchitectural blocks as a function of clock frequency and the amount of variation. With the combination of the variation model and the error model, we have VARIUS, a comprehensive model that is capable of producing detailed statistics of timing errors as a function of different process parameters and operating conditions. We propose possible applications of VARIUS to microarchitectural research.

Transistor-Level Tools for High-End Processor Custom Circuit Design at IBM

IBM's high-performance microprocessor designs leverage internally developed electronic design automation tools to create high-frequency, power efficient, and robust microprocessors. This paper describes some of the tools employed in the custom circuit design methodology in IBM. The tools described include a transistor-level block-based static timer, a static noise analysis methodology, and a transistor width tuner that optimizes performance and area. We also describe the application of electrical rule checking used to enforce consistent design practices. Finally, we discuss a macro extraction tool that determines parasitic resistance and capacitance of interconnect from a layout

Predicting communication protocol performance on superscalar architectures using instruction dependency

Increasing diversity in telecommunication workloads leads to greater complexity in communication protocols. This occurs as channel bandwidth rapidly increases. These factors result in larger computational loads for network processors that are increasingly turning to high performance microprocessor designs. This paper presents an analytical method for estimating the performance of instruction level parallel (ILP) processors executing network protocol processing applications. Instruction dependency information extracted while executing an application is used to calculate upper and lower bounds for throughput, measured in instructions per cycle (IPC). Results using UDP/TCP/IP applications show that the simulated IPC values fall between the analytically derived upper and lower bounds, validating the model. The analytical method is much less expensive than cycle-accurate simulation, but reveals similar throughput performance predictions. This allows the architectural design space for network superscalar processors to be explored more rapidly and comprehensively, to reveal the maximum IPC that is possible for a given application workload and the available hardware resources.

Integrated microarchitectures

Trends in CMOS technology point to an era of high-performance microprocessor design in which problems such as power consumption and cooling, deviceand chip-level variability, and hard and soft errors threaten to slow down historically established performance growth rates.

Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches

As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become an inevitable issue for highperformance microprocessor designs. Since on-chip caches are major contributors of the leakage, a number of researchers have proposed efficient leakage reduction techniques. However, it is still not clear that 1) what kind of algorithm can be considered and 2) how much they have impact on energy and performance. To answer these questions, we explore runtime cache management algorithm, and evaluate the energy-performance efficiency for several alternatives.

Clock generation and distribution for the first IA-64 microprocessor

The clock design for the first implementation of the IA-64 microprocessor is presented. A clock distribution with an active distributed deskewing technique is used to achieve a low skew of 28 ps. This technique is capable of compensating skews caused by within-die process variations that are becoming a significant factor of the clock design. The global, regional and local clock distributions are described. A multilevel skew budget and local clock timing methodology are used to enable a high-performance design by providing support for intentional clock skew injection and time borrowing. By providing a test access port interface to the deskew architecture and the incorporation of the on-die-clock-shrink, this design is equipped with two very powerful post-silicon timing debug tools that are critical to high-performance microprocessor design and enabled quick time-to-market.

Multiple context multithreaded superscalar processor architecture

Superscalar architecture is becoming the norm in today's high performance microprocessor design. However, achievable instruction level parallelism in programs limits the scalability of such architectures. In this paper, we introduce the Multiple Context Multithreaded Superscalar Processor (MCMS), which is an extension of conventional superscalar processor architecture to support multithreading. This is motivated by the enormous potential instruction level parallelism present in multithreaded programs. A hardware implementation of multithreaded constructs is also proposed. Results from trace-driven simulation show that with the MCMS, instruction level parallelism is indeed increased significantly. A MCMS processor with four hardware contexts can produce a speedup of up to 2.5 times over superscalar processor with similar hardware resources. We found that the primary limitation shifts from data dependencies in the superscalar processor to resource contentions in MCMS.