Hardware Architecture Design Research Articles

FPGA Accelerated Implementation of 3D Mesh Secret Sharing Based on Symmetric Similarity of Model

Secret sharing is particularly important in the field of information security, which allows for the reconstruction of secret information from secure shares. However, due to the large amount of data and non-integer data type of 3D (three-dimensional) models, it is less efficient to perform sharing compared to the 2D(two-dimensional) digital images. In order to enable efficient sharing of 3D models as well, this article designs different circuit modules to parallelize the process of sharing 3D models. The proposed structure exploits the vertex extension to perform a complete reconstruction of the 3D model. In the sharing phase, the symmetric similarity of 3D model is exploited to realize the sharing in parallel, which improves the efficiency of sharing. In the reconstruction phase, the Strassen algorithm is used to optimize matrix multiplication, which saves circuit resources. Simulation results show that the structure performs more than 100 times faster than software. The utilization of circuit resources and the size of the share are both optimized. The validity of the designed hardware architecture is confirmed after analyzing the data from experiments performed on several 3D models.

Fast rough mode decision algorithm and hardware architecture design for AV1 encoder

Fast rough mode decision algorithm and hardware architecture design for AV1 encoder

Design and Performance Evaluation of a Novel High-Speed Hardware Architecture for Keccak Crypto Coprocessor

Design and Performance Evaluation of a Novel High-Speed Hardware Architecture for Keccak Crypto Coprocessor

Design of a low-area hardware architecture to predict early signs of sudden cardiac arrests

Sudden cardiac arrest (SCA) results in an unexpected and untimely death within minutes, and its early prediction can alert cardiac patients to a timely medical diagnosis. To detect early symptoms of an SCA, the detection and classification of ventricular tachycardias (VT) are of utmost importance. In this work, a low-area yet highly accurate hardware architecture for VT classification is proposed based on the detection of premature ventricular contraction (PVC) beats. After pre-processing of the ECG signals using a wavelet-based pre-processing unit, a characteristics-matching algorithm is used to detect the PVC beats, and a low-complexity adaptive decision-based logic classifier is used to classify them into four types of VTs, namely monomorphic, polymorphic, non-sustained VT (NSVT), and sustained VT (SVT). FPGA verification of the hardware architecture for the VT classifier using the Nexys 4 DDR Artix-7 board utilizes 10.4 % of the total available resources and displays the type of VT and the number of PVCs detected to help in determining the severity of SCA and the need for medical attention. The ASIC implementation of the proposed PVC-based VT classification using the SCL 180 nm CMOS technology results in an area overhead of 0.02 mm2 and a power consumption of 3.47 μW for a high accuracy rate of 98.2 %. When compared to the existing CA detection systems for wearable devices, the proposed one consumes the least area while achieving high detection rates.

Hardware motion estimation methods survey and example real-time architecture design

Motion estimation is essential in video processing, computer vision, and other related fields due to its applications in improving data compression, enhancing image/video quality, increasing computer vision task accuracy, and conserving computational resources. Typical motion estimation methods include FS (Full Search) and DS (Diamond Search). Traditional motion estimation methods will face the challenge of high complexity in practical real-time applications. Therefore, this paper focuses on fast motion estimation algorithms and hardware architecture design for real-time applications survey and research. Aiming at the need for 1920x1080@60fps processing speed, this paper explores the key ideas of FS and DS hardware structure design based on the Vivado HLS high-level synthesis tool and provides a feasible hardware scheme to meet the real-time requirements.

An FPGA‐based tool for supporting the design, modeling, and evaluation of hybrid object recognition systems on computer engineering courses

AbstractThe field of computer vision is characterized by computationally intensive algorithms and techniques with strict real‐time requirements. Field programmable gate arrays (FPGAs) are based on a concurrent paradigm which allows the design of efficient hardware architectures and has positioned FPGAs as an ideal device for implementing compute‐intensive applications. For this reason, FPGA technology has had a great impact in areas such as computer vision, where one of the main objectives for researchers working in this field is to create efficient automatic object recognition systems. Therefore, the need to provide undergraduates with the necessary skills to design FPGA‐based object recognition systems is evident. With this aim in mind, it is essential that specialization courses related to the design of these systems include the required resources for the student to apply the theoretical knowledge in solving practical problems. In this article, we present a development tool designed to help students, teachers, and researchers during the design‐modeling‐implementation process of object recognition systems based on FPGAs. The proposed tool operates under a modular approach as this facilitates the working on any of the phases of a recognition system and it is considered as a hybrid because the other phases can be developed using a software language. An empirical evaluation involving undergraduates enrolled in a Computer Engineering program was conducted to create a hardware architecture for the DAISY descriptor that uses the homogeneous features of objects immersed in images to produce an efficient representation. By considering similar descriptors such as Scale‐Invariant Feature Transform (SIFT) and Histogram of Oriented Gradients (HOG), DAISY is computed by convolving orientation maps instead of using weighted sums of gradient norms, which offers the same kind of invariance at a lower computational cost for the dense case. The results obtained during such an evaluation indicated that students consider this FPGA‐based tool to be an alternative to receiving practical training on designing systems for solving problems related to the area of object recognition.

The Design of a High-Throughput Hardware Architecture for the AES-GCM Algorithm

The Design of a High-Throughput Hardware Architecture for the AES-GCM Algorithm

Adaptive Pipeline Hardware Architecture Design and Implementation for Image Lossless Compression/Decompression Based on JPEG-LS

Adaptive Pipeline Hardware Architecture Design and Implementation for Image Lossless Compression/Decompression Based on JPEG-LS

Fast Linear Equation Solving Algorithm and its Pipelined Hardware Architecture Design for VVC Affine Motion Estimation

Fast Linear Equation Solving Algorithm and its Pipelined Hardware Architecture Design for VVC Affine Motion Estimation

Variable Block Size Fractional Motion Estimation Hardware Architecture for VVC and HEVC Standards

The ever-increasing growth in digital video consumption motivates the research and development of new video coding standards to improve coding efficiency. Among the several new tools that the Versatile Video Coding (VVC) standard introduced lies the Quadtree Plus Multi-Type Tree (QT+MTT), which improves upon the quadtree of High Efficiency Video Coding (HEVC) in terms of coding efficiency. Nevertheless, such improvements come at the cost of increased complexity. Hence, to meet the real-time and energy efficiency requirements, embedded devices must adopt techniques to effectively reduce the VVC complexity, including customized hardware accelerators. This work presents a low-energy hardware architecture design for the Fractional Motion Estimation (FME), one of the most critical steps of HEVC and VVC encoders. The proposed architecture supports the Switchable Interpolation Filter (SIF) of VVC and was synthesized to enable Variable Block Size (VBS) from 8×8 up to 128×128 sized blocks so that it can perform the FME of most partitions of the QT+MTT from VVC. The results show increases of at most 4.52% in area and 10.79% in total power for the extra hardware needed to support VBS, and up to 9.15% and 15.72%, in area and power, respectively, for supporting up to 128×128 block sizes.

Design of spiking neural network architecture based on dendritic computation principles

The paper presents the hardware architecture design of a spiking neural network (SNN) based on dendritic computation principles. The integration of active dendritic properties into the neuronal structure of SNN aims to minimize the number of functional blocks required for hardware implementation, including synaptic connections and neurons. The available memory on the neuromorphic architecture imposes limitations on implementation, hence the need to reduce the number of functional blocks. As a test task for the SNN based on dendritic computations, we selected the image classification of eight symbols, consisting of digits one through eight. These symbols are depicted as 3×7 pixel, 1-bit images. Active dendritic properties were analyzed using the “delay plasticity” [1] principle, which introduces the mechanism of adjusting input signal delays in spiking neuron inputs. We designed an SNN model with complementary delay inputs, referred to as the active dendrite SNN, as a principle implementation. Input spikes arriving at the primary inputs are duplicated to the delay inputs after a modifiable time delay. For convenience, each delay input was set at a single value. The input images were scanned sequentially. The neural network received three direct and three inverse inputs from the six main inputs that were coded with spikes corresponding to three pixels of a string. An “on” pixel was coded with a spike arriving at a direct input, while an “off” pixel was coded with a spike arriving at the corresponding inverse input. The line scanning time was 10 μs, input width was 1 μs, and delay time was 5 μs. The optimization of spiking neuron parameters was performed through a stochastic search algorithm based on simulated annealing. The parameters optimized for the Leaky-Integrate-and-Fire (LIF) neurons included the leakage time constant (22.8 μs), firing threshold (1150 arbitrary units), and refractory period (1 μs). The active dendrite SNN training employed the tempotron learning rule [2]. The training optimized the following parameters: the maximum change in synaptic weight on potentiation and depression (0.7 and –3 arbitrary units, respectively) and the synaptic weight’s upper bound (195 arbitrary units). Complementary delayed inputs facilitated the learning of the order in which input patterns arrived for SNN neurons during training. The paper compares an SNN architecture based on dendritic computations to our previously designed two-layer SNN with a hidden perceptron layer and an output layer consisting of LIF neurons [3]. Using the same LIF neuron design, input image coding, and LIF neuron layer structure as in the proposed architecture, our two-layer SNN with a hidden perceptron layer and output layer of LIF neurons successfully recognized 3×5 images of three symbols with only 10 neurons and 63 synapses. Alternatively, the active dendrite SNN was able to recognize 3×7 images of eight symbols with four neurons and 48 synaptic weights. In conclusion, incorporating active dendrite properties into the SNN architecture for image recognition resulted in optimized functional block usage, lowering the number of neurons and synapses used by 60 and 24%, respectively.

A Survey of Hardware Self-Organizing Maps.

Self-organizing feature maps (SOMs) are commonly used technique for clustering and data dimensionality reduction in many application fields. Indeed, their inherent property of topology preservation and unsupervised learning of processed data without any prior knowledge put them in the front of candidates for data reduction in the Internet of Things (IoT) and big data (BD) technologies. However, the high computational cost of SOMs limits their use to offline approaches and makes the online real-time high-performance SOM processing more challenging and mostly reserved to specific hardware implementations. In this article, we present a survey of hardware (HW) SOM implementations found in the literature so far: the most widely used computing blocks, architectures, design choices, adaptation, and optimization techniques that have been reported in the field of hardware SOMs. Moreover, we give an overview of main challenges and trends for their ubiquitous adoption as hardware accelerators in many application fields. This article is expected to be useful for researchers in the areas of artificial intelligence, hardware architecture, and system design.

Supervised learning and pattern recognition in photonic spiking neural networks based on MRR and phase-change materials

Traditional computers are limited by the separation of memory and processor units, is difficult to achieve fast, efficient, and low-power computing. While photonic spiking neural networks (SNNs) can overcome these shortcomings, they encounter limitations in large-scale integration. Silicon photonics platform, compatible with mature Complementary Metal Oxide Semiconductor (CMOS) platforms, is a promising candidate for realizing large-scale photonic SNNs. In this work, we proposed an integrated photonic SNN by exploiting the photonic properties of phase-change material (PCM) Ge2Sb2Te5 (GST) and micro-ring resonators (MRR), and demonstrated its integrate-and-fire (IF) behavior. Based on a system-level behavioral model, we adopt an improved Tempotron-like ReSuMe supervised learning algorithm to train the proposed photonic SNNs and complete a pattern recognition task for the clock's 12 clockwise directions. Then the influence of different noise levels is considered, and the accuracy is close to 1 when the noise level is less than 0.2. We propose a photonic implementation of such an SNN system, and use wavelength division multiplexing to achieve a scalable architecture for the pattern recognition task. The collaborative design and optimization of hardware architecture and algorithm are realized, providing a theoretical basis for the realization of photonic SNN based on MRRs and PCM.

Towards Critical Industrial Wireless Control: Prototype Implementation and Experimental Evaluation on URLLC

Ultra reliable low latency communication (URLLC) is a promising technology to enable critical industrial wireless control, such as tactile sensing and motion control. This article presents a novel software-defined URLLC prototype and establishes a human-in-loop robotic teleoperation platform for experimental evaluations. First, by studying the control and communication requirements of robotic teleoperation, the key challenges for URLLC-based industrial wireless control are analyzed. Then, the prototype development including protocol stack and hardware architecture design is introduced in detail, and extensive experiments are performed to evaluate the communication latency and control transparency for robotic teleoperation. Experimental results show that the prototype can realize millisecond-level latency with ultra-high reliability, and support wireless teleoperation with similar transparency as wired teleoperation. Finally, challenges and future research issues towards 6G are discussed.

Contact force regulation in physical human-machine interaction based on model predictive control

AbstractWith increasing attention to physical human-machine interaction (pHMI), new control methods involving contact force regulation in collaborative and coexistence scenarios have spread in recent years. Thanks to its internal robustness, high dynamic performance, and capabilities to avoid constraint violations, a Model Predictive Control (MPC) action can pose a viable solution to manage the uncertainties involved in those applications. This paper uses an MPC-driven control method that aims to apply a well-defined and tunable force impulse on a human subject. After describing a general control design suitable to achieve this goal, a practical implementation of such a logic, based on an MPC controller, is shown. In particular, the physical interaction considered is the one occurring between the body of a patient and an external perturbation device in a dynamic posturography trial. The device prototype is presented in both its hardware architecture and software design. The MPC-based main control parameters are thus tuned inside hardware-in-the-loop and human-in-the-loop environments to get optimal behaviors. Finally, the device performance is analyzed to assess the MPC algorithm’s accuracy, repeatability, flexibility, and robustness concerning the several uncertainties due to the specific pHMI environment considered.

Motion estimation algorithm and architecture survey

Motion estimation is a key part of video temporal characteristics analysis including video filter and compression. Increasing requirements for high-quality video image processing have confirmed the necessity of researching motion estimation. Current motion estimation methods, including high-efficient fast motion estimation algorithms and hardware architecture designs, achieved different performances from different perspectives. In this paper, we focus on analyzing typical fast algorithms and hardware architecture designs for motion estimation, comparing the used methods, and pointing out the basic ideas of motion estimation research schemes. In terms of theoretical implications, the research contributed to a more comprehensive reference for fast motion estimation algorithms and their hardware architecture designs.

Automatic Generation of Spatial Accelerator for Tensor Algebra

Tensor algebra finds applications in various domains including machine learning applications, data analytics and others. Spatial hardware accelerators are widely used to boost the performance of tensor algebra applications. It has a complex hardware architecture and rich design space. Prior approaches based on manual implementation lead to low programming productivity, making it hard to explore the large design space. In this paper, we propose Tensorlib, a framework for generating spatial hardware accelerators for tensor algebra applications. Tensorlib is motivated by the observation that, tensor dataflows can be expressed with linear transformations, and they share common hardware modules which can be reused across different designs. Tensorlib first uses Space-Time Transformation to explore different dataflows, which can compactly represent the hardware dataflow using a transformation matrix. Next, we identify the common structures of different dataflows and build parameterized hardware module templates. Our generation framework can select the needed hardware modules for each dataflow, connect the modules using a specified interconnection pattern, and automatically generate the complete hardware accelerator design. Tensorlib remarkably improves the productivity for the development and optimization of spatial hardware architecture, providing a rich design space with trade-offs in performance, area, and power. Experiments show that Tensorlib can automatically generate hardware designs with different dataflows for a variety of tensor algebra programs. Tensorlib can achieve 318 MHz frequency and 786 GFLOP/s throughput for matrix multiplication kernel on Xilinx VU9P FPGA, which outperforms the state-of-the-art generators.

Hardware architecture design for real-time SIFT extraction with reduced memory usage

Hardware architecture design for real-time SIFT extraction with reduced memory usage

TRIM: A Design Space Exploration Model for Deep Neural Networks Inference and Training Accelerators

There is increasing demand for specialized hardware for training deep neural networks, both in edge/IoT environments and in high performance computing systems. The design space of such hardware is very large due to the wide range of processing architectures, deep neural network configurations, and dataflow options. This makes developing deep neural network processors quite complex, especially for training. We present TRIM, an infrastructure to help hardware architects explore the design space of deep neural network accelerators for both inference and training in the early design stages. The model evaluates at the whole network level, considering both inter-layer and intra-layer activities. Given applications, essential hardware specifications, and a design goal, TRIM can quickly explore different hardware design options, select the optimal dataflow and guide new hardware architecture design. We validated TRIM with FPGA-based implementation of deep neural network accelerators and ASIC-based architectures. We also show how to use TRIM to explore the design space through several case studies. TRIM is a powerful tool to help architects evaluate different hardware choices to develop efficient inference and training architecture design. Experimental results show that TRIM is a powerful tool for rapidly exploring the design space of DNN architectures for training and inference.

Hardware architecture design for complementary ensemble empirical mode decomposition algorithm

In this paper, we have presented a field-programmable gate array (FPGA) as well as an application-specific integrated circuit (ASIC) based design for the complementary ensemble empirical mode decomposition (CEEMD) algorithm. CEEMD is an adaptive signal analysis method that decomposes an input signal into many signals, each of which is termed an intrinsic mode function (IMF). In this work, the CEEMD architecture is developed in the form of Verilog-HDL code. The ASIC is designed by using a 180 nm technology library. Our proposed ASIC can be operated at a clock rate of 58.82 MHz, and the total power dissipation of the ASIC is 76.20 mW. The core area of the CEEMD ASIC is 1.53 mm2. The FPGA-based design of CEEMD can work with a clock rate of 50 MHz, and Virtex-7 FPGA is used for the implementation purpose. The proposed parallel architecture of CEEMD extensively reduces the computational time of the design by employing parallel processing. FPGA and the ASIC-based design of CEEMD have very less computation time and can be used for real-time applications.